公开(公告)号：US06916701B2

公开(公告)日：2005-07-12

申请号：US10235773

申请日：2002-09-05

Applicant: Chang Hun Han

Inventor： Chang Hun Han

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8246 ,  H01L23/52 ,  H01L27/088 ,  H01L27/10 ,  H01L27/105 ,  H01L27/112 ,  H01L21/8239

CPC classification number: H01L27/11266 ,  H01L27/105 ,  H01L27/11293

Abstract: Disclosed is a method for fabricating a silicide layer of a flat cell memory device. The disclosed method comprises the steps of: providing a silicon substrate whereon a flat cell array region and a peripheral circuit region are defined; forming a word line and a bit diffusion layer on the flat cell array region of the substrate and a word line and source/drain junction on the peripheral circuit region; forming a gap fill insulating layer to fill up the gap between the word lines; removing the gap fill insulating layer on the peripheral circuit region; forming an insulating layer on the whole substrate; dry etching the insulating layer to expose a surface of word line, and a surface of the substrate of the peripheral circuit region, thereby forming a spacer on a side wall of the word line of the peripheral circuit region; and forming a silicide layer on the upper part of the word line of the flat cell array region and, at the same time, forming a salicide layer on the upper part of the word line and the surface of the substrate of the peripheral circuit region.

Abstract translation: 公开了一种制造扁平单元存储器件的硅化物层的方法。 所公开的方法包括以下步骤：提供限定扁平单元阵列区域和外围电路区域的硅衬底; 在基板的平坦单元阵列区域上形成字线和位扩散层，并在外围电路区域上形成字线和源极/漏极结; 形成间隙填充绝缘层以填满字线之间的间隙; 去除外围电路区域上的间隙填充绝缘层; 在整个基板上形成绝缘层; 干蚀刻绝缘层以露出字线的表面和外围电路区域的基板的表面，由此在外围电路区域的字线的侧壁上形成间隔物; 在平坦单元阵列区域的字线的上部形成硅化物层，同时在字线的上部和外围电路区域的基板的表面上形成自对准硅化物层。