公开(公告)号：US08932912B2

公开(公告)日：2015-01-13

申请号：US13945535

申请日：2013-07-18

申请人： Broadcom Corporation

发明人： Akira Ito ,  Xiangdong Chen

IPC分类号： H01L21/82 ,  H01L29/78 ,  H01L27/112 ,  H01L23/525 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/7816 ,  H01L21/76224 ,  H01L23/5252 ,  H01L27/088 ,  H01L27/11206 ,  H01L27/11226 ,  H01L27/1124 ,  H01L27/11246 ,  H01L27/11266 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.

摘要翻译： 根据一个实施例，具有横向扩散的金属氧化物半导体（LDMOS）结构的一次性可编程（OTP）器件包括包括通过栅电极和通过栅极电介质的通过栅极，以及包括编程门 电极和编程栅极电介质。 编程门通过LDMOS结构的漏极扩展区与通过栅极间隔开。 当用于将编程栅极电介质破裂的编程电压施加到编程栅电极时，LDMOS结构为通路提供保护。 一种用于制造这种OTP器件的方法包括形成漏极延伸区域，在漏极延伸区域的第一部分上制造栅极通孔，以及在漏极延伸区域的第二部分上制造编程栅极。

公开(公告)号：US20140151815A1

公开(公告)日：2014-06-05

申请号：US14130470

申请日：2012-08-02

申请人： Kai HUANG ,  Peng DU ,  Jianxiang CAI ,  Tsung-nten HSU

发明人： Kai HUANG ,  Peng DU ,  Jianxiang CAI ,  Tsung-nten HSU

IPC分类号： H01L27/112

CPC分类号： H01L27/112 ,  H01L27/0207 ,  H01L27/11266

摘要： A read-only memory includes a plurality of storage units arranged in an array. The read-only memory includes two kinds of storage units with different structures, the two kinds of storage units with different structures are a first MOS transistor and a second MOS transistor. A source and a drain of the first MOS transistor have the same type, a source and a drain of the second MOS transistor have inverse type. These two kinds of MOS transistors can be used to store binary 0 and 1 respectively. In the manufacturing method of the read-only memory, the same type of drain and source can be manufactured simultaneously, no extra mask plate is needed, so the extra mask plate of a conventional read-only memory can be saved.

摘要翻译： 只读存储器包括以阵列排列的多个存储单元。 只读存储器包括具有不同结构的两种存储单元，具有不同结构的两种存储单元是第一MOS晶体管和第二MOS晶体管。 第一MOS晶体管的源极和漏极具有相同类型，第二MOS晶体管的源极和漏极具有相反的类型。 这两种MOS晶体管可分别用于存储二进制0和1。 在只读存储器的制造方法中，可以同时制造相同类型的漏极和源极，不需要额外的掩模板，因此可以节省常规只读存储器的额外掩模板。

公开(公告)号：US08053342B2

公开(公告)日：2011-11-08

申请号：US12836066

申请日：2010-07-14

申请人： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young-Ho Kim ,  Myung-Jo Chun ,  Jung-Ho Moon

发明人： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young-Ho Kim ,  Myung-Jo Chun ,  Jung-Ho Moon

IPC分类号： H01L21/8238

CPC分类号： H01L27/105 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1052 ,  H01L27/11266 ,  H01L27/11293

摘要： A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.

摘要翻译： 可以稳定地输出数据的掩模只读存储器（ROM）装置包括接通电池和截止电池。 开放单元包括衬底上的孔上栅极结构和衬底内的电池单元结结构。 离子电池包括在衬底上的离子电池栅极结构和衬底内的细胞外结合结构。 单体栅极结构包括单元间栅极绝缘膜，单晶体栅极电极和单元间栅极间隔物。 该单电池结结构包括具有第一极性的第一和第二开孔离子注入区和第二极性的第三和第四接通电离子注入区。 离群栅极结构包括离子栅极绝缘膜，离子阱栅极电极和非电池栅极间隔物。 离电池结结构包括具有第一极性的第一和第二离子外离子注入区域和第二极性的第三离子间离子注入区域。

公开(公告)号：US07466578B2

公开(公告)日：2008-12-16

申请号：US11604960

申请日：2006-11-28

申请人： David B. Scott ,  Radu Avramescu

发明人： David B. Scott ,  Radu Avramescu

IPC分类号： G11C17/00

CPC分类号： G11C17/10 ,  H01L27/0207 ,  H01L27/112 ,  H01L27/11226 ,  H01L27/11266

摘要： One embodiment of the present invention relates to a read only memory (ROM) that includes a memory cell pair. The memory cell pair includes a first memory cell and a second memory cell that share a common drain that is associated with the memory cell pair. The memory cell also includes a bitline configured to provide data from the first and second memory cells, wherein the bitline is electrically isolated from the common drain. Other methods and systems are also disclosed.

摘要翻译： 本发明的一个实施例涉及一种包括存储单元对的只读存储器（ROM）。 存储单元对包括共享与存储单元对相关联的公共漏极的第一存储单元和第二存储单元。 存储单元还包括配置成从第一和第二存储器单元提供数据的位线，其中位线与公共漏极电隔离。 还公开了其它方法和系统。

公开(公告)号：US20080123388A1

公开(公告)日：2008-05-29

申请号：US11604960

申请日：2006-11-28

申请人： David B. Scott ,  Radu Avramescu

发明人： David B. Scott ,  Radu Avramescu

IPC分类号： G11C17/00

CPC分类号： G11C17/10 ,  H01L27/0207 ,  H01L27/112 ,  H01L27/11226 ,  H01L27/11266

摘要： One embodiment of the present invention relates to a read only memory (ROM) that includes a memory cell pair. The memory cell pair includes a first memory cell and a second memory cell that share a common drain that is associated with the memory cell pair. The memory cell also includes a bitline configured to provide data from the first and second memory cells, wherein the bitline is electrically isolated from the common drain. Other methods and systems are also disclosed.

公开(公告)号：US07364973B2

公开(公告)日：2008-04-29

申请号：US11882656

申请日：2007-08-03

申请人： Hyun-Khe Yoo ,  Weon-ho Park ,  Byoung-ho Kim

发明人： Hyun-Khe Yoo ,  Weon-ho Park ,  Byoung-ho Kim

IPC分类号： H01L21/8234

CPC分类号： H01L27/11266 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11293

摘要： A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.

摘要翻译： 一种制造NOR型掩模ROM器件的方法包括在第一导电类型的半导体衬底上形成用于OFF电池的第一栅电极和用于ON电池的第二栅电极。 为了对掩模ROM器件进行编码，通过将与第一导电类型相反的第二导电类型的杂质注入到仅与第一栅电极的一侧相邻并且邻近第二侧的半导体衬底中来形成多个源极/漏极区域 的第二栅电极。 为了防止与接触区域的位线接触孔不对准，仅将额外的杂质注入到掩模ROM器件区域的位线接触区域中。 当形成在与掩模ROM器件相同的衬底上的半导体器件包括双扩散区域时，可以同时实现两者的附加注入。

公开(公告)号：US20050035414A1

公开(公告)日：2005-02-17

申请号：US10642077

申请日：2003-08-14

申请人： Bomy Chen ,  Kai Yue ,  Andrew Chen

发明人： Bomy Chen ,  Kai Yue ,  Andrew Chen

IPC分类号： G11C11/56 ,  G11C17/00 ,  G11C17/12 ,  H01L21/8236 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113

CPC分类号： H01L27/11266 ,  G11C11/5671 ,  G11C11/5692 ,  G11C17/123 ,  H01L27/112

摘要： A multi-bit Read Only Memory (ROM) cell has a semiconductor substrate of a first conductivity type with a first concentration. A first and second regions of a second conductivity type spaced apart from one another are in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. The ROM cell has one of a plurality of N possible states, where N is greater than 2. The possible states of the ROM cell are determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.

摘要翻译： 多位只读存储器（ROM）单元具有第一导电类型的具有第一浓度的半导体衬底。 彼此间隔开的第二导电类型的第一和第二区域在衬底中。 通道在第一和第二区域之间。 通道具有三个部分，第一部分，第二部分和第三部分。 门间隔开并与通道的至少第二部分绝缘。 ROM单元具有多个N个可能状态中的一个，其中N大于2. ROM单元的可能状态由存在或不存在在通道的第一部分中形成的延伸或光晕而相邻 到与第二区域相邻的第一区域和/或在该通道的第三部分中。 在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。

公开(公告)号：US06590266B1

公开(公告)日：2003-07-08

申请号：US10064906

申请日：2002-08-28

申请人： Mu-Yi Liu ,  Tso-Hung Fan ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Tso-Hung Fan ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H01L2994

CPC分类号： H01L27/11266 ,  H01L27/112

摘要： A 2-bit mask ROM device and a fabrication method thereof are described. The 2-bit mask ROM device includes a substrate; a gate structure, disposed on a part of the substrate; a 2-bit code region, configured in the substrate beside both sides of the gate structure; at least one spacer, disposed on both sides of the gate structure; a buried drain region, configured in the substrate beside both sides of the spacer; a doped region, configured in the substrate between the buried drain region and the 2-bit code region, wherein the dopant type of the doped region is different from that for the 2-bit code region and the dopant concentration in the doped region is higher than that in the 2-bit code region; an insulation layer, disposed above the buried drain region; and a word line disposed on the gate structures along a same row.

摘要翻译： 描述2位掩模ROM器件及其制造方法。 2位掩模ROM器件包括衬底; 栅极结构，设置在所述衬底的一部分上; 2位代码区，配置在栅极结构的两侧旁边的基板中; 设置在所述栅极结构的两侧的至少一个间隔物; 掩埋漏极区域，被构造在所述衬底旁边的所述间隔物的两侧; 掺杂区域，配置在掩埋漏极区域和2位码区域之间的衬底中，其中掺杂区域的掺杂剂类型与2位码区域的掺杂区域不同，并且掺杂区域中的掺杂剂浓度更高 比在2位代码区域; 绝缘层，设置在所述掩埋漏极区域的上方; 以及沿同一行设置在栅极结构上的字线。

公开(公告)号：US06512276B1

公开(公告)日：2003-01-28

申请号：US09624888

申请日：2000-07-24

申请人： Takao Tanaka

发明人： Takao Tanaka

IPC分类号： H01L2976

CPC分类号： H01L27/11266 ,  H01L27/112 ,  Y10S257/905 ,  Y10S257/907

摘要： In a mask ROM, bit lines 1 composed of a diffused region formed in a semiconductor substrate are formed in such a zigzag pattern that in a region where each of the bit lines overlaps word lines 2 formed of a patterned conductive film formed on an oxide film covering the diffused region of the bit lines 1, the bit line is perpendicular to the word lines, and in a region where each of the bit lines does not overlap the word lines, the bit line has a predetermined angle to the word lines, with the result that channel regions of memory cell transistors are located in a checker pattern. Thus, it is possible to minimize influence of a code ion implanted impurity diffused region 3A to a low-threshold memory cell transistor C.

摘要翻译： 在掩模ROM中，形成在半导体衬底中的扩散区域所构成的位线1以这样的之字形形式形成，即在每个位线与形成在氧化膜上的图案化导电膜形成的字线2重叠的区域中形成 覆盖位线1的扩散区域，位线垂直于字线，并且在每个位线不与字线重叠的区域中，位线与字线具有预定的角度，与 存储单元晶体管的通道区域位于检验器图案中的结果。 因此，可以将代码离子注入杂质扩散区域3A的影响最小化到低阈值存储单元晶体管C。

公开(公告)号：US06487119B2

公开(公告)日：2002-11-26

申请号：US09852789

申请日：2001-05-11

申请人： Noboru Egawa ,  Hitoshi Kokubun

发明人： Noboru Egawa ,  Hitoshi Kokubun

IPC分类号： G11C1134

CPC分类号： H01L27/11266 ,  G11C11/5692 ,  G11C17/126 ,  H01L27/112 ,  H01L27/11233

摘要： The mask ROM for storing quaternary data that enables a short turn around time, makes refining cell sizes simple, and that enables stable reading of data. Gaps are formed between word lines in the memory cell transistors and two n+ diffusion areas. n+ impurities are doped into these gaps in accordance with quaternary write data when data is written. A current runs between these diffusion areas only when one of these two areas into which impurities have been doped is used as a drain. Accordingly, quaternary data can be read by reading once when one diffusion area is a source and the other diffusion area is a drain and by reading again when the first diffusion area is used as a drain and the other as a source.

摘要翻译： 用于存储能够实现短周转时间的四进制数据的掩模ROM使得精细单元尺寸简单，并且能够稳定地读取数据。 在存储单元晶体管和两个n +扩散区域中的字线之间形成间隙。 当写入数据时，根据四进制写数据将n +杂质掺杂到这些间隙中。 只有当这两个掺杂有杂质的两个区域中的一个被用作漏极时，电流在这些扩散区域之间运行。 因此，当一个扩散区域是源极并且另一个扩散区域是漏极时，通过读取一次可以读取四元数据，并且当第一扩散区域用作漏极而另一个作为源时，可以再次读取四进制数据。