公开(公告)号：US20080033552A1

公开(公告)日：2008-02-07

申请号：US11596853

申请日：2005-05-17

Applicant: Sang-ho Lee ,  Ho-yeong Kang ,  Jeang-sub Park ,  Seung-hwa Yoo

Inventor： Sang-ho Lee ,  Ho-yeong Kang ,  Jeang-sub Park ,  Seung-hwa Yoo

IPC: A61B17/70

CPC classification number: A61B17/7053 ,  A61B17/7062

Abstract: Provided is an intervertebral implant which is fixedly placed between spinous processes of adjacent vertebrae to maintain a predetermined space between the spinous processes and to prevent a relative displacement between superior and inferior facets of adjacent vertebrae. The intervertebral implant includes a spacer having two opposing notches for receiving two adjacent spinous processes and a band for securing the two spinous processes and the spacer, the spacer comprising a through-hole bored through sides of the spacer to allow the band to pass therethrough and depressions curved inwardly from outsides of the spacer to facilitate fastening of the band passed through the through-hole, and the band binding the two spinous processes and the spacer in a figure 8 form while passing through the through-hole to secure the two spinous processes and the spacer.

Abstract translation: 提供了一种椎间植入物，其固定地放置在相邻椎骨的棘突之间以保持棘突之间的预定空间并且防止相邻椎骨的上下面之间的相对位移。 椎间植入物包括具有用于接收两个相邻棘突的两个相对的凹口的间隔物和用于固定两个棘突和间隔物的带，所述间隔件包括穿过间隔物的侧面的通孔，以允许带穿过， 从间隔物的外侧向内弯曲的凹陷以便于穿过通孔的带的紧固，并且带状结合图8中的两个棘突和间隔物，同时穿过通孔以固定两个棘突 和间隔物。

公开(公告)号：US07203160B1

公开(公告)日：2007-04-10

申请号：US09666054

申请日：2000-09-20

Applicant: Sang Ho Lee

Inventor： Sang Ho Lee

IPC: G01R31/08

CPC classification number: H04L43/0817

Abstract: A duplexing control system and method of an ATM switching system capable of carrying out a stable switching of duplexing with a simple circuit construction is disclosed. The system has two boards respectively having a first interface matching with an input bus so as to interface received ATM cell, a second interface matching with an output bus so as to interface a transmitted ATM cell, an SAR for disassembling and assembling data units contained in an application layer in the transmitted/received ATM cell by a unit of ATM cell, a control section for controlling general operation in order to maintain the active state according to data processing information contained in a signal applied from the cell disassembling and assembling circuit, when the its own board is endowed with the active authority by the signal, and a DRAM for storing data transmitted/received for the switching of duplexing between the boards. The duplexing control system and method in an ATM system causes data processing information of one board and a duplexing authority to be formed into an ATM cell and to be transferred through a cell bus, so that a duplexing control can be stably carried out.

Abstract translation: 公开了一种能够以简单的电路结构实现双工的稳定切换的ATM交换系统的双工控制系统和方法。 该系统具有两个板，分别具有与输入总线匹配的第一接口，以便接收接收到的ATM信元，与输出总线匹配的第二接口，以便接收所发送的ATM信元，用于拆卸和组合包含在其中的数据单元 通过ATM信元单元发送/接收的ATM信元中的应用层，控制部分，用于控制一般操作，以便根据包含在从信元拆卸和组装电路施加的信号中的数据处理信息来保持活动状态，当时 其自己的板被信号赋予主动权限，以及用于存储用于在板之间切换双工的发送/接收数据的DRAM。 ATM系统中的双工控制系统和方法使一个电路板和双工部门的数据处理信息形成为一个ATM信元，并通过一个信元总线进行传输，从而可以稳定地进行双工控制。

公开(公告)号：US20070007327A1

公开(公告)日：2007-01-11

申请号：US11334815

申请日：2006-01-18

Applicant: Ok-Hwan Kim ,  Sang-Ho Lee

Inventor： Ok-Hwan Kim ,  Sang-Ho Lee

IPC: B26D7/01

CPC classification number: B26F1/36 ,  B26D3/10 ,  B26D7/2628 ,  B26D2007/0056 ,  B26D2007/0087 ,  B26F1/02 ,  B26F1/14 ,  B26F1/32 ,  B26F1/46 ,  Y10T83/8785 ,  Y10T83/8831 ,  Y10T83/8841 ,  Y10T83/943 ,  Y10T83/944

Abstract: Rotary punching apparatus includes: an upper rotation plate provided with punching member on which punching blade having a pattern of a specific shape is formed, and an upper jig which support elastically the punching member and forms a guide hole in the same shape as the pattern; an upper plate configured to enable the upper rotation plate to be rotated; a lower rotation plate including lower jig on which a punching hole in the same shape as the pattern is formed; and lower plate configured to enable the lower rotation plate to be rotated. The upper and the lower plate are provided with at least one magnets in a position opposite to each other and the upper and the lower rotation plate are provided with at least one or more magnets in a position opposite to each other, so that the fixed position is mutually aligned due to the magnetic force of the magnet. As a result, the present invention can freely punch a desired position irrespective of punching positions such as the seat as an object of the punching.

Abstract translation: 旋转冲孔装置包括：上旋转板，其上形成有形成具有特定形状的图案的冲压刀片的冲压构件;弹性地支撑冲压构件并形成与图案相同形状的引导孔的上夹具; 配置成使上部旋转板旋转的上板; 下部旋转板包括下部夹具，其上形成与图案相同形状的冲孔; 并且下板被配置为使得下旋转板能够旋转。 上板和下板在彼此相对的位置设置有至少一个磁体，并且上下旋转板在彼此相对的位置中设置有至少一个或多个磁体，使得固定位置 由于磁体的磁力而相互对准。 结果，本发明可以自由地冲压期望的位置，而不管冲孔位置如作为冲孔的对象的座。

公开(公告)号：USD527366S1

公开(公告)日：2006-08-29

申请号：US29224845

申请日：2005-03-09

Applicant: Sang Ho Lee

Designer： Sang Ho Lee

公开(公告)号：US06670253B2

公开(公告)日：2003-12-30

申请号：US10265723

申请日：2002-10-08

Applicant: Sang-Ho Lee

Inventor： Sang-Ho Lee

IPC: H01L21336

CPC classification number: H01L29/66636 ,  H01L27/10873 ,  H01L29/0653 ,  H01L29/41766

Abstract: A semiconductor device and a fabrication method thereof which can, for example, prevent a punch-through from occurring by forming oxide spacers around source/drain regions in a semiconductor substrate instead of forming a conventional halo ion implanting layer. Such structure improves, for example, an operational speed by reducing junction capacitance, prevents a hot carrier effect from occurring by weakening an electric field around the drain region, and improves reliability by preventing a latch up from occurring. The semiconductor device includes a gate electrode formed on the semiconductor substrate, sidewall spacers formed at the sidewalls of the gate electrode, an impurity layer formed in the semiconductor substrate below each sidewall spacer, a trench formed in the semiconductor substrate at both sides of the gate electrode, oxide spacers formed at the bottom inside corner of each trench, and a conductive material filling up each trench.

公开(公告)号：US06631266B1

公开(公告)日：2003-10-07

申请号：US09391704

申请日：1999-09-08

Applicant: Sang-ho Lee ,  Byung-chul You

Inventor： Sang-ho Lee ,  Byung-chul You

IPC: H04Q736

CPC classification number: H04W16/18 ,  H04W16/24

Abstract: A method for determining a coverage area according to antenna patterns in a sector base station system provided that the antenna gain of the omni base station is identical to the antenna gain of the sector base station. The method includes the steps of calculating the ratio of the coverage area of the sector base station to the omni base station, calculating the coverage area of the omni base station considering a handover area, and multiplying the calculated ratio of coverage area of the sector base station by the calculated coverage area of the omni base station, to determine the number of base stations required in designing the wireless network by the operator.

Abstract translation: 一种用于根据扇区基站系统中的天线方向图来确定覆盖区域的方法，只要全向基站的天线增益与扇区基站的天线增益相同即可。 该方法包括以下步骤：计算扇区基站的覆盖区域与全向基站的比率，计算考虑到切换区域的全基站的覆盖区域，并将计算出的扇区基础覆盖区域的比率 通过计算的全站仪的覆盖区域来确定由操作者设计无线网络所需的基站的数量。

公开(公告)号：US06483158B1

公开(公告)日：2002-11-19

申请号：US09481495

申请日：2000-01-12

Applicant: Sang-Ho Lee

Inventor： Sang-Ho Lee

IPC: H01L2976

CPC classification number: H01L29/66636 ,  H01L27/10873 ,  H01L29/0653 ,  H01L29/41766

Abstract: A semiconductor device and a fabrication method thereof which can, for example, prevent a punch-through from occurring by forming oxide spacers around source/drain regions in a semiconductor substrate instead of forming a conventional halo ion implanting layer. Such structure improves, for example, an operational speed by reducing junction capacitance, prevents a hot carrier effect from occurring by weakening an electric field around the drain region, and improves reliability by preventing a latch up from occurring. The semiconductor device includes a gate electrode formed on the semiconductor substrate, sidewall spacers formed at the sidewalls of the gate electrode, an impurity layer formed in the semiconductor substrate below each sidewall spacer, a trench formed in the semiconductor substrate at both sides of the gate electrode, oxide spacers formed at the bottom inside corner of each trench, and a conductive material filling up each trench.

Abstract translation: 半导体器件及其制造方法，其可以例如通过在半导体衬底中的源极/漏极区域周围形成氧化物间隔来防止穿通而不是形成常规的卤素离子注入层。 这样的结构例如通过减小结电容来提高操作速度，通过削弱漏极区域周围的电场来防止热载流子效应的发生，并且通过防止发生闩锁来提高可靠性。 半导体器件包括形成在半导体衬底上的栅极电极，形成在栅极侧壁处的侧壁间隔物，形成在半导体衬底中的每个侧壁间隔物下方的杂质层，形成在栅极两侧的半导体衬底中的沟槽 电极，形成在每个沟槽的底部内角处的氧化物间隔物，以及填充每个沟槽的导电材料。

公开(公告)号：US5966420A

公开(公告)日：1999-10-12

申请号：US908571

申请日：1997-08-08

Applicant: Sang Ho Lee

Inventor： Sang Ho Lee

IPC: G11C11/413 ,  H03K21/00

CPC classification number: H03K21/00

Abstract: A counter circuit uses a plurality of counter circuits so as to be used in all products employing a counter circuit in a semiconductor device, and thereby performs a multi-bit linear burst sequence operation. The counter circuit for embodying a linear burst sequence includes: a low order counting means which responds to an external clock signal and an external counting control signal, receives and counts a least significant first bit data among base input signals having bits ranging from a first bit to a N-th bit, and then generates a first data signal and a first high order control signal; and a plurality of high order counting means which receive bits ranging from a second bit successively connected to the least significant first bit to N-th bit, perform a counting operation, and generate a second data signal and a second high order control signal. The high order counting means which responds to the high order control signal and the counting control signal which are generated from the high order counting means of a previous bit of a present input bit, performs a counting operation, and outputs data signal.

Abstract translation: 计数器电路使用多个计数器电路，以便在半导体器件中采用计数器电路的所有产品中使用，从而执行多位线性突发序列操作。 用于实现线性突发序列的计数器电路包括：响应于外部时钟信号的一个低阶计数装置和一个外部计数控制信号，在基本输入信号中接收和计数最低有效的第一位数据，该基本输入信号具有从第一位 到第N位，然后产生第一数据信号和第一高阶控制信号; 以及多个高阶计数装置，其接收从连续连接到最低有效第一比特到第N比特的第二比特的比特，执行计数操作，并产生第二数据信号和第二高阶控制信号。 响应于从当前输入位的先前位的高位计数装置产生的高阶控制信号和计数控制信号的高阶计数装置执行计数操作，并输出数据信号。

公开(公告)号：US5937283A

公开(公告)日：1999-08-10

申请号：US974281

申请日：1997-11-19

Applicant: Sang-Ho Lee

Inventor： Sang-Ho Lee

IPC: H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/70

CPC classification number: H01L29/78645 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78624 ,  H01L29/78642

Abstract: A thin film transistor and a method for fabricating the same in which a self alignment method is used to form an offset area and source and drain electrodes are disclosed, the TFT including a substrate; a trench formed in the substrate,; an active layer fromed on the substrate and on the trench; a gate insulating film formed on the active layer; a gate electrode formed on the gate insulating film on at least one side of the trench; a source region formed in the active layer on a bottom side of the trench; and drain regions formed in the active layer on the substrate to be isolated form the gate electrode.

Abstract translation: 公开了一种薄膜晶体管及其制造方法，其中使用自对准方法来形成偏移区域和源极和漏极，所述TFT包括衬底; 形成在衬底中的沟槽; 在衬底上和沟槽上的有源层; 形成在有源层上的栅极绝缘膜; 在所述沟槽的至少一侧上形成在所述栅极绝缘膜上的栅电极; 形成在所述沟槽的底侧上的所述有源层中的源极区域; 以及形成在待隔离的基板上的有源层中的漏极区域形成栅电极。

公开(公告)号：US5877988A

公开(公告)日：1999-03-02

申请号：US901433

申请日：1997-07-25

Applicant: Jae Kwang Shim ,  Sang Ho Lee

Inventor： Jae Kwang Shim ,  Sang Ho Lee

IPC: G06F12/16 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C16/04

CPC classification number: G11C7/1078 ,  G11C7/22

Abstract: A write error preventing circuit for a semiconductor memory device prevents an erroneous reading operation an input buffer compares an externally applied write enable signal to an effective level signal, which is preset therein. A write error preventive circuit outputs a disable signal to the input buffer during an interval of time when a ground voltage bounces in accordance with an internal output signal from a NAND gate of an output buffer. The circuit prevents the outputting of a write signal from the input buffer during a read operation in accordance with the internal output signal from the output buffer when the ground voltage bounces.

Abstract translation: 用于半导体存储器件的写入错误防止电路防止错误读取操作，输入缓冲器将外部施加的写使能信号与其中预设的有效电平信号进行比较。 写入错误防止电路在接地电压根据来自输出缓冲器的与非门的内部输出信号反弹的时间间隔期间向输入缓冲器输出禁止信号。 当接地电压反弹时，该电路根据来自输出缓冲器的内部输出信号，在读取操作期间防止从输入缓冲器输出写入信号。