公开(公告)号：US11474871B1

公开(公告)日：2022-10-18

申请号：US16582958

申请日：2019-09-25

Applicant: XILINX, INC.

Inventor： Millind Mittal ,  Jaideep Dastidar

IPC: G06F9/50 ,  G06F12/0815 ,  G06F9/455 ,  G06F9/38

Abstract: The embodiments herein describe a virtualization framework for cache coherent accelerators where the framework incorporates a layered approach for accelerators in their interactions between a cache coherent protocol layer and the functions performed by the accelerator. In one embodiment, the virtualization framework includes a first layer containing the different instances of accelerator functions (AFs), a second layer containing accelerator function engines (AFE) in each of the AFs, and a third layer containing accelerator function threads (AFTs) in each of the AFEs. Partitioning the hardware circuitry using multiple layers in the virtualization framework allows the accelerator to be quickly re-provisioned in response to requests made by guest operation systems or virtual machines executing in a host. Further, using the layers to partition the hardware permits the host to re-provision sub-portions of the accelerator while the remaining portions of the accelerator continue to operate as normal.

公开(公告)号：US11456951B1

公开(公告)日：2022-09-27

申请号：US17225737

申请日：2021-04-08

Applicant: Xilinx, Inc.

Inventor： Chunhua Wu

IPC: G06F15/173 ,  H04L45/00 ,  H04L45/42 ,  H04L45/02

Abstract: Modifying a flow table for a network accelerator can include, in response to determining that a flow table of a network accelerator does not include any rules corresponding to first packet data of a first flow received from a network, forwarding the first packet data to a host computer. Subsequent to the flow table being updated to include a new rule for the first flow, for second packet data of the first flow received from the network, the second packet data can be processed using the new rule. The second packet data can be queued. In response to receiving the first packet data from the host computer, the first packet data can be processed using the new rule. The processed packet data can be forwarded to a destination port followed by the queued second packet data.

公开(公告)号：US20220292042A1

公开(公告)日：2022-09-15

申请号：US17199197

申请日：2021-03-11

Applicant: XILINX, INC.

Inventor： Steven Leslie POPE ,  Derek Edward ROBERTS ,  Dmitri KITARIEV ,  Neil Duncan TURTON ,  David James RIDDOCH ,  Ripduman SOHAN

IPC: G06F13/40 ,  G06F9/48

Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.

公开(公告)号：US11425231B2

公开(公告)日：2022-08-23

申请号：US17037468

申请日：2020-09-29

Applicant: Xilinx, Inc.

Inventor： Steve Pope ,  Kieran Mansley ,  Sian James ,  David J. Riddoch

IPC: H04L29/08 ,  H04L1/00 ,  H04L12/931 ,  H04L69/322 ,  H04L49/60 ,  H04L69/32

Abstract: Data is received at a buffer used by a protocol processing stack which protocol processes the received data. The received data is made available to, for example, an application, before the protocol processing of the data is complete. If the protocol processing is successful, the data made available to the application is committed.

公开(公告)号：US11425036B1

公开(公告)日：2022-08-23

申请号：US16386127

申请日：2019-04-16

Applicant: Xilinx, Inc.

Inventor： Jaime Herrera ,  Gordon J. Brebner ,  Ian McBryan ,  Rowan Lyons

IPC: H04L45/74 ,  H04L69/22 ,  H04L47/56 ,  H04L45/24

Abstract: A match-action circuit includes one or more conditional logic circuits, each having an input coupled to input header or metadata of a network packet, and each configured to generate an enable signal as a function of one or more signals of the header or metadata. Each match circuit of one or more match circuits is configured with response values associated with key values. Each match circuit is configured to conditionally lookup response value(s) associated with an input key value from the header or metadata in response to the enable signal from a conditional logic circuit. One or more action circuits are configured to conditionally modify, in response to states of the response value(s) output from the match circuit(s), data of the header or the metadata.

公开(公告)号：US11405617B1

公开(公告)日：2022-08-02

申请号：US16880542

申请日：2020-05-21

Applicant: Xilinx, Inc.

Inventor： Akrum Elkhazin

IPC: H04N19/13 ,  G06F17/18 ,  H04N19/172 ,  H04N19/146

Abstract: Methods and systems for improving encoding of a picture or a frame are disclosed. According to one embodiment, a method for encoding video frames includes receiving for a frame, several binarized symbols that include a number of bins corresponding to one or more contexts. For each context from one or more contexts, the method includes entropy encoding in a first pass bins associated with the context using an initial probability distribution for the context; generating counts of zeros and ones in a set of bins associated with the context; updating the initial probability distribution using the respective counts of zeros and ones, to obtain an updated probability distribution; and entropy encoding in a second pass the bins associated with the context using the updated probability distribution, to provide at least a part of an encoded bitstream.

公开(公告)号：US20220231889A1

公开(公告)日：2022-07-21

申请号：US17665477

申请日：2022-02-04

Applicant: XILINX, INC.

Inventor： Hongtao ZHANG ,  Winson LIN ,  Arianne ROLDAN ,  Yohan FRANS ,  Geoff ZHANG

IPC: H04L25/03 ,  H03L7/089 ,  H04L27/01

Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.

公开(公告)号：US11388270B1

公开(公告)日：2022-07-12

申请号：US16401099

申请日：2019-05-01

Applicant: Xilinx, Inc.

Inventor： Veerender Kumar Soma ,  Ajay V. Sharma ,  Sunil K. Pattanaik

IPC: H04L12/26 ,  H04L69/24 ,  H04L69/28 ,  H04L69/18

Abstract: A physical (PHY) circuit can include a Physical Medium Dependent (PMD) circuit, the PMD circuit having a receiver and a transmitter, a Physical Medium Attachment (PMA) circuit coupled to the PMD circuit, and a plurality of Physical Coding Sublayer (PCS) circuits coupled to the PMA circuit, wherein each PCS circuit is configured to implement a different communication protocol. The PHY circuit can also include an auto-negotiation circuit coupled to the PMD circuit, wherein the auto-negotiation circuit is configured to determine a selected communication protocol compatible with a link partner device from a plurality of communication protocols by configuring the receiver to operate at different data rates over time, the different data rates corresponding to different ones of the plurality of communication protocols.

公开(公告)号：US11386644B2

公开(公告)日：2022-07-12

申请号：US15786267

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Elliott Delaye ,  Ashish Sirasao ,  Aaron Ng ,  Yongjun Wu ,  Jindrich Zejda

IPC: G06V10/94 ,  G06F3/06 ,  G06F17/15 ,  G06N3/04 ,  G06N3/063 ,  G06T1/20 ,  G06T1/60 ,  G06V10/44

Abstract: An example preprocessor circuit includes: a first buffer configured to store rows of image data and output a row thereof; a second buffer, coupled to the first buffer, including storage locations to store respective image samples of the row output by the first buffer; shift registers; an interconnect network including connections, each connection coupling a respective one of the shift registers to more than one of the storage locations, one or more of the storage locations being coupled to more than one of the connections; and a control circuit configured to load the shift registers with the image samples based on the connections and shift the shift registers to output streams of image samples.

公开(公告)号：US11375050B1

公开(公告)日：2022-06-28

申请号：US17019039

申请日：2020-09-11

Applicant: XILINX, INC.

Inventor： Millind Mittal ,  Jaideep Dastidar ,  Kiran Puranik

IPC: H04L69/18

Abstract: Embodiments herein describe a layer converter that includes a proxy legacy interface that permits the layers for a legacy interconnect protocol to be recycled without any modifications, thus achieving legacy functionality alongside the new protocols' layer implementation. Put differently, the layer converter permits the layers of the legacy interconnect protocol to be reused to permit data to be transmitted on a link shared with data transmitted using a new interconnect protocol.