公开(公告)号：US20140304563A1

公开(公告)日：2014-10-09

申请号：US14314430

申请日：2014-06-25

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318558 ,  G01R31/318572

Abstract: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.

公开(公告)号：US20140258799A1

公开(公告)日：2014-09-11

申请号：US14281189

申请日：2014-05-19

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/318541 ,  G01R31/318555 ,  G01R31/318586

Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.

Abstract translation: 集成电路具有知识产权核心。 知识产权核心包括测试访问端口39，测试数据输入引线15，测试数据输出引线13，控制引线17和存在的外部寄存器ERP导线37.扫描寄存器25包含知识产权核心和ERP引导线37携带 指示存在扫描寄存器的信号。

公开(公告)号：US20140250342A1

公开(公告)日：2014-09-04

申请号：US14279989

申请日：2014-05-16

Applicant: Texas Instruments Incorporated

Inventor： Jayashree Saxena ,  Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/31721 ,  G01R31/318563 ,  G01R31/318575 ,  G01R31/318577 ,  G06F1/3234

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract translation: 扫描架构通常用于测试集成电路中的数字电路。 本发明描述了一种使常规扫描架构适应于低功率扫描架构的方法。 低功耗扫描架构保持常规扫描架构的测试时间，同时要求比传统扫描架构明显更低的运行能力。 低功耗扫描架构对于IC /模具制造商是有利的，因为它允许并行测试嵌入在IC /管芯中的更多数量的电路（例如DSP或CPU核心电路），而不会消耗IC /管芯内的太多功率 。 由于低功耗扫描架构降低了测试功耗，因此可以使用传统的扫描架构在以前可能的同时测试晶片上的更多裸片。 这允许减少晶片测试时间，这降低了晶片上每个芯片的制造成本。

公开(公告)号：US08826090B2

公开(公告)日：2014-09-02

申请号：US14162976

申请日：2014-01-24

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/3177 ,  G06F11/267 ,  G01R31/317

CPC classification number: G01R31/31723 ,  G01R31/317 ,  G01R31/31705 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/318591 ,  G01R31/318597 ,  G06F11/267

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract translation: 本公开描述了使用JTAG Tap的TMS和/或TCK终端作为通用串行输入/输出（I / O）曼彻斯特编码通信终端。 Tap的TMS和/或TCK终端可以用作串行I / O通信通道; （1）IC和外部控制器，（2）在第一和第二IC之间，或（3）IC内的第一和第二核心电路之间。 如上所述，使用TMS和/或TCK端子作为串行I / O通道不会影响JTAG Tap的标准化操作，因为TMS和/或TCK I / O操作发生在Tap被放置在 非活跃稳态。

公开(公告)号：US20140245090A1

公开(公告)日：2014-08-28

申请号：US14268073

申请日：2014-05-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/2851 ,  G01R31/31715 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318555 ,  G01R31/318563 ,  G01R31/31919

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together. The scan distributor and collector circuits can be formed in core circuits (704). The core circuits then can be connected to other core circuits and functional circuits with simple connections to the parallel scan circuits through the scan distributor and collector circuits.

Abstract translation: 具有并行扫描路径（824-842,924-942）的集成电路（70）包括一对或一对扫描分配器（800,900）和扫描收集器（844,944）电路。 扫描路径将激励测试数据应用于集成电路上的功能电路（702），并从功能电路接收响应测试数据。 扫描分配器电路（800）从外围接合焊盘（802）接收串行测试数据，并将其分配到每个并行扫描路径。 扫描收集器电路（844）从并行扫描路径收集测试数据并将其应用于外围接合焊盘（866）。 这使得更长的并行扫描路径能够连接到功能电路。 扫描分配器和集电极电路可以分别串联连接以提供并行连接到更平行的扫描路径。 此外，多路复用器电路（886,890）可以选择性地将成对的扫描分配器和集电极电路连接在一起。 扫描分配器和集电极电路可以形成在核心电路（704）中。 然后，核心电路可以通过扫描分配器和集电极电路与并行扫描电路的简单连接连接到其他核心电路和功能电路。

公开(公告)号：US20140229781A1

公开(公告)日：2014-08-14

申请号：US14258691

申请日：2014-04-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318561 ,  G01R31/318563 ,  G01R31/318572

Abstract: An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

Abstract translation: 集成电路可以具有多个核心电路，每个核心电路具有在IEEE标准1149.1中定义的测试访问端口。 这些端口的访问和控制是一个测试链接模块。 集成电路上的测试访问端口可以以一个测试链接模块来控制对多个辅助测试链接模块和测试访问端口的访问的层次结构。 每个次级测试链接模块依次也可以控制对三级测试链接模块和测试访问端口的访问。 测试链接模块也可用于仿真。

公开(公告)号：US20140215283A1

公开(公告)日：2014-07-31

申请号：US14231967

申请日：2014-04-01

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318505 ,  G01R31/318555 ,  G06F11/267

Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Abstract translation: IC包括IEEE 1149.1标准测试接入端口（TAP）接口和附加的片外TAP接口。 片外TAP接口连接到另一个IC的TAP。 芯片TAP接口可以通过IC上的TAP链接模块来选择。

公开(公告)号：US08749258B2

公开(公告)日：2014-06-10

申请号：US13657115

申请日：2012-10-22

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3187

CPC classification number: G01R31/2851 ,  G01R31/31715 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318555 ,  G01R31/318563 ,  G01R31/31919

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together. The scan distributor and collector circuits can be formed in core circuits (704). The core circuits then can be connected to other core circuits and functional circuits with simple connections to the parallel scan circuits through the scan distributor and collector circuits.

Abstract translation: 具有并行扫描路径（824-842,924-942）的集成电路（70）包括一对或一对扫描分配器（800,900）和扫描收集器（844,944）电路。 扫描路径将激励测试数据应用于集成电路上的功能电路（702），并从功能电路接收响应测试数据。 扫描分配器电路（800）从外围接合焊盘（802）接收串行测试数据，并将其分配到每个并行扫描路径。 扫描收集器电路（844）从并行扫描路径收集测试数据并将其应用于外围接合焊盘（866）。 这使得更长的并行扫描路径能够连接到功能电路。 扫描分配器和集电极电路可以分别串联连接以提供并行连接到更平行的扫描路径。 此外，多路复用器电路（886,890）可以选择性地将成对的扫描分配器和集电极电路连接在一起。 扫描分配器和集电极电路可以形成在核心电路（704）中。 然后，核心电路可以通过扫描分配器和集电极电路与并行扫描电路的简单连接连接到其他核心电路和功能电路。

公开(公告)号：US20140157071A1

公开(公告)日：2014-06-05

申请号：US14173492

申请日：2014-02-05

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel ,  Joel J. Graber

IPC: G01R31/3185

CPC classification number: G01R31/318544 ,  G01R31/31721 ,  G01R31/3177 ,  G01R31/318541 ,  G01R31/318547 ,  G01R31/318575 ,  G01R31/31858 ,  G01R31/318586

Abstract: Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.

Abstract translation: 扫描和扫描BIST架构通常用于测试集成电路中的数字电路。 本公开改进了低功率扫描和扫描BIST方法。 该改进允许低功耗扫描和扫描BIST架构实现与传统扫描和Scan-BIST架构中使用的延迟测试功能一样有效的延迟测试功能。

公开(公告)号：US08726110B2

公开(公告)日：2014-05-13

申请号：US13765194

申请日：2013-02-12

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/318505 ,  G01R31/318555 ,  G06F11/267

Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Abstract translation: IC包括IEEE 1149.1标准测试接入端口（TAP）接口和附加的片外TAP接口。 片外TAP接口连接到另一个IC的TAP。 芯片TAP接口可以通过IC上的TAP链接模块来选择。