公开(公告)号：US20170132754A1

公开(公告)日：2017-05-11

申请号：US15143491

申请日：2016-04-29

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Brian Chae ,  Shashank Dabral ,  Niraj Nandan ,  Hetul Sanghvi

IPC: G06T3/40 ,  G06T1/60 ,  G06T1/20

Abstract: An apparatus for scaling images is provided that includes at least two input ports, a scaling component coupled to the at least two input ports, the scaling component including a plurality of scalers, the scaling component configurable to map any scaler to any input port of the at least two input ports and configurable to map more than one scaler to any input port, and a memory coupled to the at least two input ports and to outputs of the plurality of scalers, the memory configured to store image data for each input port and scaled image data output by the plurality of scalers.

公开(公告)号：US09473784B2

公开(公告)日：2016-10-18

申请号：US14279318

申请日：2014-05-16

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/89 ,  H04N19/14 ,  H04N19/82 ,  H04N19/436 ,  H04N19/176 ,  H04N19/117 ,  H04N19/186 ,  H04N19/182 ,  H04N19/423 ,  H04N19/102

CPC classification number: H04N19/436 ,  H04N19/117 ,  H04N19/14 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186 ,  H04N19/423 ,  H04N19/82

Abstract: A method for sample adaptive offset (SAO) filtering of largest coding units (LCUs) of a video frame in an SAO component is provided that includes receiving, by the SAO component, an indication that deblocked pixel blocks of an LCU are available, and applying SAO filtering, by the SAO component, to each pixel block of pixel blocks of an SAO processing area corresponding to the LCU responsive to the indication, wherein pixels of each pixel block of the SAO processing area are filtered in parallel.

Abstract translation: 提供了一种用于在SAO组件中的视频帧的最大编码单元（LCU）的采样自适应偏移（SAO）滤波的方法，其包括由SAO组件接收到LCU的解块像素块可用的指示，以及应用 通过SAO分量对SAO处理区域的对应于该LCU的SAO处理区域的每个像素块进行SAO滤波，其中SAO处理区域的每个像素块的像素被并行地滤波。

公开(公告)号：US20150304648A1

公开(公告)日：2015-10-22

申请号：US14607053

申请日：2015-01-27

Applicant: Texas Instruments Incorporated

Inventor： Rahul Gulati ,  Vasant Easwaran ,  Mihir Narendra Mody ,  Prashant Dinkar Karandikar ,  Prithvi Y.A. Shankar ,  Aishwarya Dubey ,  Kedar Chitnis ,  Rajat Sagar

IPC: H04N17/00 ,  G06T7/00

CPC classification number: H04N17/002 ,  G06T7/0002 ,  G06T2207/30168 ,  G06T2207/30252

Abstract: A method for testing an imaging subsystem of a system-on-a-chip (SOC) is provided that includes executing imaging subsystem test software instructions periodically on a processor of the SOC, receiving reference image data in the imaging subsystem responsive to the executing of the test software instructions, performing image signal processing on the reference image data by the imaging subsystem to generate processed reference image data, and using the processed reference image data by the test software instructions to verify whether or not the imaging subsystem is operating correctly.

Abstract translation: 提供了一种用于测试片上系统（SOC）的成像子系统的方法，其包括在所述SOC的处理器上周期性地执行成像子系统测试软件指令，响应于所述成像子系统的执行而接收所述成像子系统中的参考图像数据 测试软件指令，由成像子系统对参考图像数据执行图像信号处理，以生成经处理的参考图像数据，以及通过测试软件指令使用经处理的参考图像数据来验证成像子系统是否正确地操作。

公开(公告)号：US20140362928A1

公开(公告)日：2014-12-11

申请号：US13950042

申请日：2013-07-24

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Chaitanya S. Ghone ,  Joseph Meehan

IPC: H04N19/86 ,  H04N19/593 ,  H04N19/503 ,  H04N19/44 ,  H04N19/91

CPC classification number: H04N19/86 ,  H04N19/42 ,  H04N19/44 ,  H04N19/82

Abstract: A VP8 video decoder is implemented by partitioning the required functions across multiple sub systems, with an optimal mapping to existing functional blocks. Key optimizations include the reuse of hardware designed for prior generation V̂6 and VP7 decoders. In order to reduce implementation complexity, cost and power consumption, a non exact, approximate deblocking loop filter is implemented.

Abstract translation: VP8视频解码器通过跨多个子系统划分所需的功能，并与现有的功能块进行最佳映射来实现。 关键优化包括为先前的V6和VP7解码器设计的硬件的重用。 为了降低实现的复杂性，成本和功耗，实现了非精确的近似去块环路滤波器。

公开(公告)号：US20140341271A1

公开(公告)日：2014-11-20

申请号：US14282211

申请日：2014-05-20

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/117 ,  H04N19/176 ,  H04N19/50 ,  H04N19/13 ,  H04N19/107 ,  H04N19/119 ,  H04N19/124 ,  H04N19/60

CPC classification number: H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/186 ,  H04N19/82 ,  H04N19/86

Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

Abstract translation: 提供了一种解封处理视频的过滤方法。 经处理的视频包括多个块，并且每个块包括多个子块。 多个块中的当前块包括垂直边缘和水平边缘。 经处理的视频还包括一组对应于当前块的控制参数和重构像素。 在当前块的垂直边缘和水平边缘估计边界强度指数。 加载控制参数集合，对应于当前块的重构像素和对应于一组相邻子块的部分滤波像素。 基于边界强度指数和控制参数集合对当前块的垂直边缘和水平边缘进行滤波，使得在对当前块的至少一个水平边缘进行滤波之前对当前块的垂直边缘进行滤波。

公开(公告)号：US20140232938A1

公开(公告)日：2014-08-21

申请号：US13769480

申请日：2013-02-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody

IPC: H04N7/24

CPC classification number: H04N21/234309 ,  H04N19/12 ,  H04N19/136

Abstract: Several systems and methods for processing of video frames based on one or more video formats are disclosed. In an embodiment, a video processing system comprises a memory and a video engine. The memory stores a plurality of video frames, a primary set of instructions and a plurality of secondary sets of processing instructions. Each secondary set of processing instructions is associated with a video format. The video engine is loaded with the primary set of instructions and is configured to fetch one or more video frames and a secondary set of processing instructions from the memory based on the loaded primary set of instructions. The fetched secondary set of processing instructions corresponds to a video format determined for processing of the one or more video frames. The video engine performs processing of the one or more video frames based on the secondary set of processing instructions.

Abstract translation: 公开了一种用于基于一种或多种视频格式处理视频帧的系统和方法。 在一个实施例中，视频处理系统包括存储器和视频引擎。 存储器存储多个视频帧，主要指令集和多个辅助的处理指令集合。 每个次要处理指令集与视频格式相关联。 视频引擎被加载有主要指令集，并且被配置为基于所加载的主要指令集从存储器获取一个或多个视频帧和辅助的一组处理指令。 所获取的次要处理指令集对应于为一个或多个视频帧的处理确定的视频格式。 视频引擎基于第二组处理指令执行一个或多个视频帧的处理。

公开(公告)号：US12256108B2

公开(公告)日：2025-03-18

申请号：US17367387

申请日：2021-07-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Chaitanya S. Ghone ,  Joseph Meehan

IPC: H04N19/86 ,  H04N19/42 ,  H04N19/44 ,  H04N19/82

Abstract: A video decoder system, in one embodiment, includes one or more processors and a memory storing instructions that when executed by the one or more processors cause the video decoding system to perform an entropy decoding operation in a frame level pipelined manner on a bitstream representative of encoded video data to produce first output data, perform at least one of an inverse quantization operation or an inverse frequency transform operation in a row level pipelined manner on the first output data to produce second output data, perform a deblocking filtering operation on first input data that includes the second output data in a row level pipelined manner to produce third output data, and output a decoded video output based on the third output data.

公开(公告)号：US12242377B2

公开(公告)日：2025-03-04

申请号：US18496178

申请日：2023-10-27

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Kishon Vijay Abraham Israel Vijayponraj ,  Mihir Narendra Mody ,  Vijaya Rama Raju Kanumuri ,  Cory Dean Stewart

IPC: G06F12/00 ,  G06F9/46 ,  G06F12/02 ,  G06F12/06

Abstract: Transaction mappers, methods and systems are provided. An example transaction mapper includes a table that associates virtual identification values with bus-device-function (BDF) values; and a firewall that receives an input-output request including a first virtual identification value of the virtual identification values, the first virtual identification value being associated with a function of an external peripheral, generates a first BDF value and a first traffic class value based on the table and the first virtual identification value, determine whether the first virtual identification value satisfies a threshold range, and determine whether to forward the input-output request to an external host device based on whether the first virtual identification value satisfies the threshold range.

公开(公告)号：US12170780B2

公开(公告)日：2024-12-17

申请号：US18369315

申请日：2023-09-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hrushikesh Tukaram Garud ,  Mihir Narendra Mody ,  Soyeb Nagori

IPC: H04N19/86 ,  H04N19/117 ,  H04N19/147 ,  H04N19/149 ,  H04N19/176 ,  H04N19/182 ,  H04N19/82

Abstract: The disclosure provides a sample adaptive offset (SAO) encoder. The SAO encoder includes a statistics collection (SC) block and a rate distortion optimization (RDO) block coupled to the SC block. The SC block receives a set of deblocked pixels and a set of original pixels. The SC block categorizes each deblocked pixel of the set of deblocked pixels in at least one of a plurality of band and edge categories. The SC block estimates an error in each category as difference between a deblocked pixel of the set of deblocked pixels and corresponding original pixel of the set of original pixels. The RDO block determines a set of candidate offsets associated with each category and selects a candidate offset with a minimum RD cost. The minimum RD cost is used by a SAO type block and a decision block to generate final offsets for the SAO encoder.

公开(公告)号：US12143729B2

公开(公告)日：2024-11-12

申请号：US17538833

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Gang Hua ,  Mihir Narendra Mody ,  Niraj Nandan ,  Shashank Dabral ,  Rajasekhar Reddy Allu ,  Denis Roland Beaudoin

IPC: H04N23/84 ,  H04N9/67 ,  H04N9/68

Abstract: A technique for image processing, comprising: receiving input image data, wherein the image data is companded into a first bit depth, wherein the image data includes incomplete color values for pixels of the image data, and wherein the image data is associated with a first color space, interpolating the image data to generate color values for the incomplete color values for pixels of the image data, expanding the image data from the first bit depth to a second bit depth, wherein the color values of the expanded image data have a linear dynamic range, and wherein the second bit depth is higher than the first bit depth, converting the color values for pixels of the expanded image data from the first color space to a second color space, and compressing the color values for pixels of the image data to a third bit depth, the third bit depth lower than the second bit depth, and wherein the compressed color values have a nonlinear dynamic range.