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    Fault tolerant synchronizer
    1.
    发明授权
    Fault tolerant synchronizer 有权

    公开(公告)号：US11255905B2

    公开(公告)日：2022-02-22

    申请号：US16152531

    申请日：2018-10-05

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Denis Roland Beaudoin ,  Samuel Paul Visalli

    IPC: G01R31/317 ,  G01R31/3177 ,  H03K3/037 ,  H03K19/21

    Abstract: A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.

    Fault tolerant synchronizer
    3.
    发明授权
    Fault tolerant synchronizer 有权

    公开(公告)号：US11796592B2

    公开(公告)日：2023-10-24

    申请号：US17573683

    申请日：2022-01-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Denis Roland Beaudoin ,  Samuel Paul Visalli

    IPC: G01R31/317 ,  H03K3/037 ,  G01R31/3177 ,  H03K19/21 ,  G01R31/34

    CPC classification number: G01R31/31726 ,  G01R31/3177 ,  G01R31/31703 ,  H03K3/037 ,  H03K19/21

    Abstract: A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.

    Method and system for in-line ECC protection
    5.
    发明授权
    Method and system for in-line ECC protection 有权

    公开(公告)号：US11119909B2

    公开(公告)日：2021-09-14

    申请号：US16590515

    申请日：2019-10-02

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Denis Roland Beaudoin ,  Ritesh Dhirajlal Sojitra ,  Samuel Paul Visalli

    IPC: G11C29/00 ,  G06F12/02 ,  G06F12/0879 ,  G11C11/409 ,  G11C29/42 ,  G06F13/40

    Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

    High precision color processing for wide dynamic range sensors
    9.
    发明授权
    High precision color processing for wide dynamic range sensors 有权

    公开(公告)号：US12143729B2

    公开(公告)日：2024-11-12

    申请号：US17538833

    申请日：2021-11-30

    Applicant: Texas Instruments Incorporated

    Inventor： Gang Hua ,  Mihir Narendra Mody ,  Niraj Nandan ,  Shashank Dabral ,  Rajasekhar Reddy Allu ,  Denis Roland Beaudoin

    IPC: H04N23/84 ,  H04N9/67 ,  H04N9/68

    Abstract: A technique for image processing, comprising: receiving input image data, wherein the image data is companded into a first bit depth, wherein the image data includes incomplete color values for pixels of the image data, and wherein the image data is associated with a first color space, interpolating the image data to generate color values for the incomplete color values for pixels of the image data, expanding the image data from the first bit depth to a second bit depth, wherein the color values of the expanded image data have a linear dynamic range, and wherein the second bit depth is higher than the first bit depth, converting the color values for pixels of the expanded image data from the first color space to a second color space, and compressing the color values for pixels of the image data to a third bit depth, the third bit depth lower than the second bit depth, and wherein the compressed color values have a nonlinear dynamic range.

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