公开(公告)号：US07636717B1

公开(公告)日：2009-12-22

申请号：US11689421

申请日：2007-03-21

Applicant: Pankaj Gupta ,  Srinivasan Venkatachary

Inventor： Pankaj Gupta ,  Srinivasan Venkatachary

IPC: G06F17/30 ,  G06F17/00

CPC classification number: G06F17/30985 ,  H04L63/1416 ,  Y10S707/99932 ,  Y10S707/99936 ,  Y10S707/99942

Abstract: A search tree embodying a plurality of signatures to be compared with an input string of characters and including a number of success transitions characterized by a success size parameter and including a number of failure transitions characterized by a failure size parameter is selectively modified to achieve a desired balance between processing speed and memory area requirements.

Abstract translation: 选择性地修改体现多个签名的搜索树，以便与输入的字符串进行比较，并且包括成功大小参数的特征，并且包括以故障大小参数为特征的多个故障转移的成功转换，以实现期望的 处理速度与内存区域要求之间的平衡。

公开(公告)号：US07589362B1

公开(公告)日：2009-09-15

申请号：US11764157

申请日：2007-06-15

Applicant: Dimitri Argyres ,  Bindiganavale S. Nataraj

Inventor： Dimitri Argyres ,  Bindiganavale S. Nataraj

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L23/585 ,  H01L27/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having a number of inputs coupled to the outputs of the MLR cells and having an output to generate a corresponding bit of the revision code. The MLR cells in each MLR group structure are assigned to different device layers, and each device layer is assigned to one MLR cell in each MLR group structure. Each revision code bit is controllable by any MLR cell in the corresponding MLR group structure.

Abstract translation: 包括衬底，形成在衬底上的多个器件层的集成电路（IC）器件以及产生指示器件修订版本的修订代码的多个多级修正（MLR）结构。 每个MLR组结构包括多个MLR单元，并且包括具有耦合到MLR单元的输出的多个输入的奇偶校验电路，并且具有用于生成修订代码的对应位的输出。 每个MLR组结构中的MLR单元被分配给不同的设备层，并且每个设备层被分配给每个MLR组结构中的一个MLR单元。 每个修订代码位可由相应MLR组结构中的任何MLR单元控制。

公开(公告)号：US07570503B1

公开(公告)日：2009-08-04

申请号：US11438185

申请日：2006-05-22

Applicant: Dinesh Maheshwari ,  Andrew Wright ,  Bin Jiang ,  Bartosz Banachowicz

Inventor： Dinesh Maheshwari ,  Andrew Wright ,  Bin Jiang ,  Bartosz Banachowicz

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns can include a first storage circuit with first and second data path, a second storage circuit with a third and fourth data path, and a compare circuit. No more than four conductive lines in a column wise direction have a direct electrical connection to the TCAM cell. Such conductive lines can include a first bit line coupled to the first data path and the third data path and a second bit line coupled to the second data path and the fourth data path.

Abstract translation: 形成在具有排列成行和列的单元的TCAM存储单元阵列中的三元内容可寻址存储器（TCAM）单元电路可以包括具有第一和第二数据路径的第一存储电路，具有第三和第四数据路径的第二存储电路，以及 比较电路。 在列方向上不超过四条导线与TCAM电池有直接电连接。 这样的导线可以包括耦合到第一数据路径和第三数据路径的第一位线和耦合到第二数据路径和第四数据路径的第二位线。

公开(公告)号：US07565481B1

公开(公告)日：2009-07-21

申请号：US10977516

申请日：2004-10-29

Applicant: Hari Om

Inventor： Hari Om

IPC: G06F12/00 ,  G06F13/00 ,  G11C15/00

CPC classification number: G11C15/00

Abstract: A content addressable memory (CAM) device (200) can provide for suppression of hit indications. Prioritized match indications (212) can be applied in parallel to both an encoding read-only-memory (ROM) (204-1) and suppression data store (206). A suppression data store (206) can output suppression bits (SH0 and SH1) that correspond to each CAM entry. Hit indications can be selectively suppressed according the values of suppression bits (SH0 and SH1). Hit suppression methods for a CAM device are also disclosed.

Abstract translation: 内容可寻址存储器（CAM）设备（200）可以提供抑制命中指示。 优先匹配指示（212）可以并行地应用于编码只读存储器（ROM）（204-1）和抑制数据存储（206）两者。 抑制数据存储（206）可以输出与每个CAM条目相对应的抑制位（SH0和SH1）。 可以根据抑制位（SH0和SH1）的值选择性地抑制命中指示。 还公开了用于CAM设备的击打抑制方法。

公开(公告)号：US07565380B1

公开(公告)日：2009-07-21

申请号：US11388785

申请日：2006-03-24

Applicant: Srinivasan Venkatachary

Inventor： Srinivasan Venkatachary

IPC: G06F12/00

CPC classification number: G06F17/30985 ,  G06F7/02 ,  G06F2207/025 ,  G06F2221/2105 ,  G06F2221/2145 ,  Y10S707/99932 ,  Y10S707/99936 ,  Y10S707/99942 ,  Y10S707/99943 ,  Y10S707/99944

Abstract: A method of modifying a finite state machine (FSM) wherein the FSM is accessed by a plurality of entries, with each entry comprised of a substring and a next-state pointer, and the FSM is modified so that each entry comprises a length, which is less than or equal to a maximum size boundary placed on a memory device configured for storing the FSM.

Abstract translation: 一种修改有限状态机（FSM）的方法，其中FSM由多个条目访问，每个条目由子字符串和下一状态指针组成，并且FSM被修改，使得每个条目包括长度，其中 小于或等于放置在配置为存储FSM的存储器件上的最大尺寸边界。

公开(公告)号：US07555593B1

公开(公告)日：2009-06-30

申请号：US11344788

申请日：2006-01-31

Applicant: Andrew Rosman

Inventor： Andrew Rosman

IPC: G06F13/10 ,  H04L12/56

CPC classification number: G06F13/4054 ,  H04L45/7453

Abstract: A CAM device having two execution pipelines includes control logic and a CAM core. The CAM core includes a plurality of independently searchable CAM arrays for storing CAM words. The control logic receives a first request that selects any number of the CAM arrays for a first compare operation, and receives a second request that selects any number of the CAM arrays for a second, separate compare operation. The control logic determines whether the same CAM array is selected by both requests. If not, the control logic schedules the first and second compare operations to be executed simultaneously in the CAM core. Otherwise, the control logic schedules the first and second compare operations for sequential executionuses a suitable arbitration technique to determine the order in which the first and second compare operations will be executed in the CAM core.

Abstract translation: 具有两个执行流水线的CAM设备包括控制逻辑和CAM内核。 CAM核包括用于存储CAM字的多个独立可搜索的CAM阵列。 所述控制逻辑接收第一请求，所述第一请求选择任何数量的所述CAM阵列用于第一比较操作，并且接收第二请求，所述第二请求选择任何数量的所述CAM阵列用于第二单独的比较操作。 控制逻辑确定两个请求是否选择相同的CAM阵列。 如果不是，则控制逻辑安排在CAM核心中同时执行的第一和第二比较操作。 否则，控制逻辑对顺序执行程序调度第一和第二比较操作适当的仲裁技术，以确定将在CAM内核中执行第一和第二比较操作的顺序。

公开(公告)号：US07505295B1

公开(公告)日：2009-03-17

申请号：US10883160

申请日：2004-07-01

Applicant: Bindiganavale S. Nataraj ,  Sandeep Khanna

Inventor： Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G11C15/00 ,  G11C7/00

CPC classification number: G11C15/00

Abstract: A content addressable memory (CAM) device having a multi-row write function. The CAM device includes a CAM array and an address circuit. The CAM array includes a plurality of CAM cells and word lines coupled to respective rows of the CAM cells. The address circuit is coupled to the CAM array and configured to activate a plurality of the word lines simultaneously to enable a write value to be stored within a selected plurality of the rows of CAM cells.

Abstract translation: 一种具有多行写入功能的内容可寻址存储器（CAM）装置。 CAM装置包括CAM阵列和地址电路。 CAM阵列包括耦合到CAM单元的相应行的多个CAM单元和字线。 地址电路耦合到CAM阵列并且被配置为同时激活多个字线，以使写入值能够存储在所选择的多个CAM单元的行中。

公开(公告)号：US07474586B1

公开(公告)日：2009-01-06

申请号：US12150146

申请日：2008-04-25

Applicant: David V. James ,  Jagadeesan Rajamanickam

Inventor： David V. James ,  Jagadeesan Rajamanickam

IPC: G11C8/00

CPC classification number: G11C15/00

Abstract: A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

Abstract translation: 公开了一种搜索引擎系统（100），其可以包括以级联配置布置的至少一个内容可寻址存储器（CAM）设备（102），其至少一个存储器设备（104），诸如静态随机存取存储器（SRAM） 。 CAM设备（102）和存储设备（104）可以通过点对点单向连接彼此连接。 由诸如网络处理单元（NPU）（110）的设备发布的命令数据可以流过从CAM设备（102）开始的所有设备，并且最终到达存储设备（104）。 存储器装置（104）可以将其自己的当前结果数据与流（例如另一RAM装置）中的先前装置的数据进行比较，并产生输出响应。

公开(公告)号：US07461200B1

公开(公告)日：2008-12-02

申请号：US10950323

申请日：2004-09-23

Applicant: Mark Birman ,  Ajay Srikrishna ,  Srinivasan Venkatachary

Inventor： Mark Birman ,  Ajay Srikrishna ,  Srinivasan Venkatachary

IPC: G06F12/00

CPC classification number: G11C15/00 ,  Y10S707/99936

Abstract: A content addressable memory device (100) and method can have CAM blocks (102-0 to 102-29) organized in block sections (104-0 to 104-6). In an overlay mode of operation, an overlay engine (106) can access an algorithmic search (SPEAR) CAM (102-28 and 102-29) to generate overlay data set search keys (keyFIB and ). Multiple data sets (e.g., FIB0, FIB1, ACL0) can be accommodated on the same CAM device by search key multiplexers (108-0 to 108-6) that selectively apply any of a number of data set search keys (keyACL , keyFIB and keyFIB ).

Abstract translation: 内容可寻址存储器件（100）和方法可以具有以块部分（104-0至104-6）组织的CAM块（102-0至102-29）。 在覆盖操作模式中，覆盖引擎（106）可以访问算法搜索（SPEAR）CAM（102-28和102-29）以生成覆盖数据集搜索关键字（keyFIB <0>和<1>）。 多个数据集（例如，FIB0，FIB1，ACL0）可以通过搜索关键多路复用器（108-0至108-6）容纳在相同的CAM设备上，该多路复用器选择性地应用多个数据集搜索键（keyACL < ，keyFIB <0>和keyFIB <1>）。

公开(公告)号：US07437354B2

公开(公告)日：2008-10-14

申请号：US10841607

申请日：2004-05-07

Applicant: Srinivasan Venkatachary ,  Pankaj Gupta ,  Anand Rangarajan

Inventor： Srinivasan Venkatachary ,  Pankaj Gupta ,  Anand Rangarajan

IPC: G06F17/30

CPC classification number: H04L45/00 ,  Y10S707/99931 ,  Y10S707/99932 ,  Y10S707/99933

Abstract: An improved architecture for a network search engine (NSE) is disclosed herein as including an interface manager, one or more levels of a splitting engine, an array of data processing units (DPUs), and a cascade block. A method for using the improved NSE architecture to form an efficient pointer entry database is also provided. As described herein, the improved NSE architecture simultaneously provides high speed, search throughput, update rate and capacity, coupled with low power and fixed latency searches for all search key widths.

Abstract translation: 网络搜索引擎（NSE）的改进的架构在此被公开为包括接口管理器，分离引擎的一个或多个级别，数据处理单元（DPU）阵列和级联块。 还提供了一种使用改进的NSE架构来形成有效的指针条目数据库的方法。 如本文所述，改进的NSE架构同时提供高速度，搜索吞吐量，更新速率和容量，以及针对所有搜索关键字宽度的低功率和固定延迟搜索。