公开(公告)号：US20070064834A1

公开(公告)日：2007-03-22

申请号：US11532686

申请日：2006-09-18

Applicant: Nobuhiro Yoshizawa

Inventor： Nobuhiro Yoshizawa

IPC: H04L27/00

CPC classification number: G06F1/0328 ,  G06F1/0342

Abstract: In order to output amplitude data with the clock frequency higher than the clock frequency of phase data, the direct digital synthesizer for transmission and detection comprises: a transmitting phase for outputting a first phase data with a first clock frequency; a curtailing unit for outputting a second phase data with a second clock frequency smaller than the first clock frequency, and outputting additional data for compensating for phase information disappeared with curtailing process; an interpolating unit for outputting a third phase data with a third clock frequency larger than the first frequency by implementing interpolating process to the second phase data, and a detecting waveform for outputting amplitude data in accordance with the third phase data. The detecting signal amplitude data can be outputted with the third clock frequency higher than the second clock frequency of the second phase data transmitted.

Abstract translation: 为了输出时钟频率高于相位数据的时钟频率的振幅数据，用于传输和检测的直接数字合成器包括：用于输出具有第一时钟频率的第一相位数据的发送相位; 用于输出具有小于第一时钟频率的第二时钟频率的第二相位数据的压缩单元，并且输出用于补偿相位信息的附加数据，该相位信息通过缩减处理消失; 内插单元，用于通过对第二相位数据进行内插处理，输出具有大于第一频率的第三时钟频率的第三相位数据;以及检测波形，用于根据第三相位数据输出幅度数据。 检测信号幅度数据可以以高于所发送的第二相数据的第二时钟频率的第三时钟频率输出。

公开(公告)号：US20070040615A1

公开(公告)日：2007-02-22

申请号：US11204674

申请日：2005-08-16

Applicant: Danny Ammar

Inventor： Danny Ammar

IPC: H03L7/00

CPC classification number: G06F1/0328 ,  G06F1/0342 ,  G06F2211/902 ,  H03L7/16

Abstract: A direct digital synthesizer (DDS) has reduced spurious signals and includes a DDS core that produces a digital representation of a signal to be synthesized. A plurality of DDS circuits are operatively connected to the DDS core, each having a digital-to-analog converter connected to the DDS core for receiving the digital representation and converting it into a signal. A modulator is operatively connected to an oscillator circuit and digital-to-analog converter for receiving signals from the digital-to-analog converter and producing a modulated output signal. The individual frequencies of the respective DDS circuits are randomly and continuously changed from each other. A mixer receives and mixes the modulated output signals from the plurality of DDS circuits to create a mixed output signal at a selected and fixed frequency.

Abstract translation: 直接数字合成器（DDS）具有减少的杂散信号，并且包括产生要合成的信号的数字表示的DDS核。 多个DDS电路可操作地连接到DDS核心，每个DDS核心具有连接到DDS核心的数模转换器，用于接收数字表示并将其转换成信号。 调制器可操作地连接到振荡器电路和数 - 模转换器，用于从数模转换器接收信号并产生调制输出信号。 相应的DDS电路的各个频率彼此随机和连续地变化。 混频器接收并混合来自多个DDS电路的调制输出信号，以选择和固定的频率创建混合输出信号。

公开(公告)号：US20060186930A1

公开(公告)日：2006-08-24

申请号：US10549940

申请日：2004-10-21

Applicant: Gunther Klage

Inventor： Gunther Klage

IPC: H03B21/00

CPC classification number: G06F1/0328 ,  H03L7/18 ,  H03L7/185

Abstract: A frequency synthesiser according to the direct digital synthesis method is provided. The frequency synthesiser includes a phase accumulator for the cyclical incrementation of a phase signal by a phase increment M present at the input of the phase accumulator, a memory unit with a table of sine-function values stored in its memory cells for the determination of sine-function values corresponding to phase values of the phase signal, a digital-to-analog converter for the conversion of time-discrete sine-function values into a quasi-analog sinusoidal time function and an anti-aliasing low-pass filter for smoothing the quasi-analog sinusoidal time function. The frequency synthesiser additionally contains an adder, which is connected between the memory unit and the digital-to-analog converter and which superimposes a non-periodic signal over the time-discrete sine-function values.

Abstract translation: 提供了一种根据直接数字合成方法的频率合成器。 频率合成器包括相位累加器，用于通过存在于相位累加器的输入端的相位增量M来循环增加相位信号;存储器单元，具有存储在其存储器单元中的正弦函数值表，用于确定正弦 - 对应于相位信号的相位值的功能值，用于将时间离散正弦函数值转换为准模拟正弦时间函数的数模转换器和用于平滑的模拟正弦时间函数的抗混叠低通滤波器 准模拟正弦时间函数。 频率合成器还包括加法器，其连接在存储器单元和数模转换器之间，并且在时间离散正弦函数值上叠加非周期信号。

公开(公告)号：US20050123078A1

公开(公告)日：2005-06-09

申请号：US10838234

申请日：2004-05-05

Applicant: Dirk Felbach

Inventor： Dirk Felbach

IPC: G06F1/04 ,  H04L27/06

CPC classification number: G06F1/04 ,  G06F1/0328

Abstract: Described is an arrangement for digital frequency synthesis with a device for phase quantization and a device for amplitude quantization, based on a reference clock and a phase increment value, wherein the device for phase quantization is followed in the signal path by a device for noise shaping of the phase. In addition, a device for noise shaping of the amplitude is provided, which follows the device for amplitude quantization in the signal path. The instant abstract is neither intended to define the invention disclosed in this specification nor intended to limit the scope of the invention in any way.

Abstract translation: 描述了基于参考时钟和相位增量值的用于相位量化的装置和用于振幅量化的装置的数字频率合成的装置，其中用于相位量化的装置在信号路径中被用于噪声整形的装置 的阶段。 此外，提供了用于振幅的噪声整形的装置，其遵循用于信号路径中的幅度量化的装置。 本摘要既不旨在限定本说明书中公开的发明，也不旨在以任何方式限制本发明的范围。

公开(公告)号：US20050093636A1

公开(公告)日：2005-05-05

申请号：US10980027

申请日：2004-11-03

Applicant: Boris Jasniewicz ,  Hartmut Keyl

Inventor： Boris Jasniewicz ,  Hartmut Keyl

IPC: G06F1/04 ,  B41F33/00 ,  B41F33/14 ,  G06F1/03 ,  H03K3/02 ,  H03K5/00 ,  H03K5/13 ,  H03L7/00 ,  H03L7/099 ,  H03L7/16 ,  H04N9/79 ,  H04N17/00

CPC classification number: H03L7/16 ,  G06F1/0328 ,  H03L7/0994

Abstract: In a circuit and a method of clock interpolation, an input signal at a first frequency is processed and at least one output signal having a second frequency being a multiple of the first frequency of the input signal is output. The circuit is defined by the fact that the input signal is measured with respect to frequency and phase in a PLL frequency measuring circuit, and by the fact that the measured input signal is multiplied by at least one frequency multiplier and an oscillator that follows the frequency multiplier.

Abstract translation: 在时钟插值的电路和方法中，处理第一频率的输入信号，并输出具有第二频率的输入信号的第一频率的倍数的至少一个输出信号。 该电路由以下事实定义：输入信号相对于PLL频率测量电路中的频率和相位被测量，并且由测量的输入信号乘以至少一个倍频器和跟随频率的振荡器 乘数。

公开(公告)号：US20050035793A1

公开(公告)日：2005-02-17

申请号：US10655898

申请日：2003-09-04

Applicant: David Shiung

Inventor： David Shiung

IPC: G06F1/03 ,  H03B21/00 ,  H03K7/00

CPC classification number: G06F1/0328

Abstract: The present invention provides an all-digital frequency synthesizer circuit using interpolation technique and Linear Feedback Shift Register (LFSR). This synthesizer adaptively outputs two sequences stored in a bank of memory, or shift register. Using the idea of interpolation, all synthesizable frequencies located between two predetermined threshold frequencies can be obtained, and resolution is determined by the order of LFSR thereby. A frequency synthesizing system is also included in the present invention.

Abstract translation: 本发明提供一种使用内插技术和线性反馈移位寄存器（LFSR）的全数字频率合成器电路。 该合成器自适应地输出存储在一组存储器或移位寄存器中的两个序列。 使用插值的思想，可以获得位于两个预定阈值频率之间的所有可合成频率，并且通过LFSR的顺序来确定分辨率。 频率合成系统也包括在本发明中。

公开(公告)号：US20050003785A1

公开(公告)日：2005-01-06

申请号：US10752085

申请日：2004-01-07

Applicant: Paul Jackson ,  Dwaine Hardy

Inventor： Paul Jackson ,  Dwaine Hardy

IPC: H03K5/156 ,  G01S7/35 ,  G06F1/03 ,  H03B28/00 ,  H03L7/18 ,  G01S13/00 ,  H04B1/06 ,  H04B7/00

CPC classification number: G01S7/35 ,  G06F1/0328 ,  G06F1/035

Abstract: A wideband signal generator according to one embodiment of the invention includes a variable frequency source and a direct digital synthesizer. Local oscillators, signal analyzers, modulators, demodulators, and other equipment including one or more such generators are also disclosed.

Abstract translation: 根据本发明的一个实施例的宽带信号发生器包括可变频率源和直接数字合成器。 还公开了本地振荡器，信号分析器，调制器，解调器和包括一个或多个这样的发生器的其它设备。

公开(公告)号：US06748407B1

公开(公告)日：2004-06-08

申请号：US09495912

申请日：2000-02-02

Applicant: Toshiyuki Oga

Inventor： Toshiyuki Oga

IPC: G06F102

CPC classification number: G06F1/0328

Abstract: A direct digital synthesizer that suppresses phase jumps which would invite the generation of spurious signals. Out of phase data supplied by a phase accumulator, the value of any rounding error arising at the time of phase computation is entered into a variable delay circuit, and the phase of a signal obtained by phase-amplitude conversion is controlled to compensate for any phase jump in the output signal.

Abstract translation: 一种直接的数字合成器，可以抑制会产生杂散信号的相位跳变。 由相位累加器提供的异相数据，在相位计算时产生的任何舍入误差的值被输入到可变延迟电路中，并且通过相位幅度转换获得的信号的相位被控制以补偿任何相位 跳入输出信号。

公开(公告)号：US06563350B1

公开(公告)日：2003-05-13

申请号：US10102111

申请日：2002-03-19

Applicant: Charles C. Warner ,  Bryan J. Dinteman

Inventor： Charles C. Warner ,  Bryan J. Dinteman

IPC: H03B2100

CPC classification number: G06F1/0328 ,  H03B28/00

Abstract: A timing signal generator including a direct digital frequency synthesizer (DDFS), a divide-by-N counter, and a pattern generator, produces a TIMING signal conveying a timed sequence of pulses. The pattern generator produces a sequence of data pairs (FREQ,N), with each pair being produced in response to each pulse of the TIMING signal and indicating a time interval that is to occur between that TIMING signal pulse and a next TIMING signal pulse. The DDFS produces an output sine wave signal (SINE) having a frequency controlled by the current FREQ data output of the pattern generator. The divide-by-N counter produces the timing signal pulses. It counts cycles of the SINE signal occurring since it last produce a TIMING signal pulse and generates a next TIMING signal when it has counted the number of SINE signal pulses indicated by the current N data output of the pattern generator.

Abstract translation: 包括直接数字频率合成器（DDFS），N分频计数器和模式发生器的定时信号发生器产生一个传送定时脉冲序列的TIMING信号。 模式发生器产生数据对序列（FREQ，N），其中每一对响应于TIMING信号的每个脉冲而产生，并且指示将在该TIMING信号脉冲和下一个TIMING信号脉冲之间发生的时间间隔。 DDFS产生具有由模式发生器的当前FREQ数据输出控制的频率的输出正弦波信号（SINE）。 N分频计数器产生定时信号脉冲。 它计算出SINE信号的周期，因为它最后产生TIMING信号脉冲并产生下一个TIMING信号，当它计数了由模式发生器的当前N个数据输出指示的SINE信号脉冲数。

公开(公告)号：US20030037081A1

公开(公告)日：2003-02-20

申请号：US10005926

申请日：2001-11-08

Inventor： Julio Alberto Vergel

IPC: G06F001/02

CPC classification number: G06F1/0328 ,  G06F1/0356

Abstract: A method, system and computer program product for digitally generating a function, including a phase accumulator configured to receive a phase value and integrate the phase value to generate an accumulation result; an address generator configured to generate consecutive addresses based on the accumulation result; a storage device configured to initiative initial digital function values based on the consecutive addresses; a coefficient calculator configured to generate coefficients for a polynomial interpolation based on the initial digital function values; and an interpolator configured to generate a final digital function value corresponding to the phase value based on the accumulation result and the coeffcients.

Abstract translation: 一种用于数字产生功能的方法，系统和计算机程序产品，包括相位累加器，其被配置为接收相位值并且积分相位值以产生累积结果; 配置为基于所述累积结果生成连续地址的地址发生器; 存储装置，被配置为基于所述连续地址来主动初始数字功能值; 系数计算器，被配置为基于初始数字函数值生成用于多项式插值的系数; 以及内插器，被配置为基于所述累积结果和所述系数来生成与所述相位值对应的最终数字函数值。