公开(公告)号：US20040267844A1

公开(公告)日：2004-12-30

申请号：US10604178

申请日：2003-06-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Riyon W. Harding ,  Karl V. Swanke ,  Sebastian T. Ventrone

IPC分类号： G06F001/02

CPC分类号： G06F7/588 ,  H04L9/0869

摘要： A random number generator (10) comprising a plurality of voltage islands (12) on a chip (14), one or more latches (16) located on each of plurality of voltage islands (12), with one or more latches (16) adapted to capture the voltage value of the respective voltage island on which they are located as an input value of one or more latches (16), a control circuit (18) for randomly controlling the state of each of plurality of voltage islands (12) and for capturing an output value for each of one or more latches (16), and a conversion circuit (20) for producing decimal numbers from the output value for each of one or more latches (16). In one embodiment, control circuit (18) includes two or more clocks (30), a multiplexer (32) for each of plurality of voltage islands (12), and an enable circuit (34) for each of plurality of voltage islands (12).

公开(公告)号：US20040220985A1

公开(公告)日：2004-11-04

申请号：US10428049

申请日：2003-05-02

发明人： John R. Morris

IPC分类号： G06F001/02

CPC分类号： G06F7/584

摘要： In a system and method for producing functions for generating pseudo-random bit sequences, an extended shift register (ESR) is formed. Each bit in the ESR is shifted to a next higher bit and the lowest-order bit is replaced with an EXCLUSIVE-OR operation of at least two other bits in the ESR. A plurality of bit equations is generated. For each bit equation, a bit in the ESR is replaced with an AND operation between shifted contents of the ESR and one of a plurality of first bit masks that isolate the bit. Each of the plurality of bit equations is combined. Shifts of the same shift distance are merged. Redundant bit masks are removed. Bit masks are transformed into bit masks comprising a sequence of zero bits and one bits. Bit masks are replaced with bit shift operations to form a function for generating the pseudo-random bit sequences.

摘要翻译： 在用于产生伪随机比特序列的功能的系统和方法中，形成扩展移位寄存器（ESR）。 ESR中的每个位被移位到下一个较高位，并且最低位被ESR中的至少两个其他位的EXCLUSIVE-OR操作替代。 生成多个位方程。 对于每个位方程，ESR中的位被ESR的移位内容与隔离该位的多个第一位掩码之一之间的“与”运算所取代。 多个位方程中的每一个被组合。 相同班次距离的换档合并。 冗余位掩码被删除。 位掩码被转换成包括零位和一位的序列的位掩码。 位掩码被替换位移操作以形成用于产生伪随机位序列的功能。

公开(公告)号：US20040210611A1

公开(公告)日：2004-10-21

申请号：US10414698

申请日：2003-04-16

发明人： Thomas L. Gradishar ,  Robert Stengel

IPC分类号： G06F001/02

CPC分类号： G06F1/025 ,  G06F2211/902

摘要： A direct digital synthesizer (30) with noise shaping circuitry can comprise a ROM-less direct digital synthesizer having a quantizer (40) and a noise shaping loop incorporating the quantizer for shaping a quantization noise due to noise from the quantizer. The noise shaping loop can comprise a noise shaping filter (44) and the noise shaping loop can feed back to the noise shaping filter a difference between an input signal (49) to the quantizer and an output signal (43) from the quantizer. The ROM-less direct digital synthesizer can further include a dither (39) combined at an input of the quantizer.

摘要翻译： 具有噪声整形电路的直接数字合成器（30）可以包括具有量化器（40）的无ROM直接数字合成器和包含量化器的噪声整形环路，用于对来自量化器的噪声造成的量化噪声进行整形。 噪声整形环路可以包括噪声整形滤波器（44），并且噪声整形环路可以将与量化器的输入信号（49）和来自量化器的输出信号（43）之间的差值反馈给噪声整形滤波器。 无ROM直接数字合成器还可以包括在量化器的输入处组合的抖动（39）。

公开(公告)号：US20040193664A1

公开(公告)日：2004-09-30

申请号：US10808240

申请日：2004-03-25

申请人： NEC ELECTRONICS CORPORATION

发明人： Shinya Shimasaki

IPC分类号： G06F001/02

CPC分类号： G06F7/582

摘要： A pseudo-random number generator comprises a linear feedback register for generating pseudo-random numbers; and a signal generator for generating a shift clock for operating a linear feedback register and predetermined input data. The linear feedback register has a plurality of registers connected in series, a first logical operation circuit for taking logical operation of output data from predetermined registers to deliver the result thereof, and a second logical operation circuit for taking logical operation of input data supplied from the outside and output data of the first logical operation circuit to supply the result thereof to any one of the registers.

摘要翻译： 伪随机数发生器包括用于产生伪随机数的线性反馈寄存器; 以及用于产生用于操作线性反馈寄存器和预定输入数据的移位时钟的信号发生器。 线性反馈寄存器具有串联连接的多个寄存器，用于对来自预定寄存器的输出数据进行逻辑运算以传递其结果的第一逻辑运算电路，以及用于从第一逻辑运算电路 外部和第一逻辑运算电路的输出数据，以将其结果提供给任何一个寄存器。

公开(公告)号：US20040083248A1

公开(公告)日：2004-04-29

申请号：US10618683

申请日：2003-07-15

申请人： NIIGATA UNIVERSITY

发明人： Yoshiaki Saito

IPC分类号： G06F007/58 ,  G06F001/02 ,  H03M001/12

CPC分类号： G06F7/588 ,  H03K3/84

摘要： During the rise time from oscillation start to steady oscillation, an electronic signal is oscillated from an oscillating means and input into an A/D converter. Then, the electronic signal is converted into digital voltage components on the magnitude of the amplitude thereof. The digital voltage components are input in a personal computer which defines a threshold level for the digital voltage components. In the personal computer, the magnitude relation between the threshold level and the digital voltage components is judged, and numeral null0null or null1null is allotted to the digital voltage components on the magnitude relation, thereby to generate a binary random number.

摘要翻译： 在从振荡开始到稳定振荡的上升时间期间，电子信号从振荡装置振荡并输入到A / D转换器。 然后，电子信号根据其幅度的大小被转换为数字电压分量。 数字电压分量输入到定义数字电压分量的阈值电平的个人计算机中。 在个人计算机中，判断阈值电平与数字电压分量之间的大小关系，并将数字“0”或“1”分配给数字电压分量，从而产生二进制随机数。

公开(公告)号：US20040049526A1

公开(公告)日：2004-03-11

申请号：US10236942

申请日：2002-09-09

发明人： Marc Joye ,  Pascal Paillier

IPC分类号： G06F001/02

CPC分类号： G06F7/72 ,  G06F2207/7204

摘要： A random prime number is generated within a predetermined interval by precalculating and storing a single value that functions as a universal parameter for generating prime numbers of any desired size. The value, null, is chosen as a product of k prime numbers. A number a is also chosen such that is co-prime with null. Once the values for null and a have been determined they can be stored and used for all subsequent iterations of the prime number generating algorithm. To generate a prime number, a random number x is chosen with uniform distribution, and a candidate prime number within the predetermined interval is calculated on the basis of the random number. This candidate is tested for primality, and returned as the result if it is prime. If the candidate is not prime, the random number x is multiplied by a, and used to generate a new candidate. This procedure is repeated, until the candidate is prime. Since a single value, namely null, needs to be precalculated, economies of storage are achieved. In addition, the interval of interest is approximated with a higher degree of resolution. Moreover, it is possible to utilize the same value of null for a number of different intervals.

摘要翻译： 通过预先计算和存储用作产生任意期望大小的素数的通用参数的单个值来在预定间隔内生成随机素数。 值pi被选为k个素数的乘积。 数字a也被选择为与pi共同配置。 一旦已经确定了pi和a的值，它们可被存储并用于素数生成算法的所有后续迭代。 为了生成素数，以均匀分布选择随机数x，并且基于随机数来计算预定间隔内的候选素数。 这个候选人被测试为原始性，如果它是素数，则作为结果返回。 如果候选者不是素数，则将随机数x乘以a，并用于生成新候选。 重复此过程，直到候选者为素数。 由于需要对单一值（即pi）进行预先计算，因此可以实现储存经济。 另外，感兴趣的间隔用更高的分辨率近似。 此外，可以使用与多个不同间隔相同的p i值。

公开(公告)号：US20040015527A1

公开(公告)日：2004-01-22

申请号：US10417374

申请日：2003-04-16

发明人： Sundararajan Sriram ,  Vijay Sundararajan

IPC分类号： G06F001/02

CPC分类号： G06F7/584 ,  G06F7/724 ,  H04J13/0022 ,  H04J13/10

摘要： The invention solves the problem of efficiently generating pseudo noise sequences with an arbitrary offset delay. Novel and improved architectures are used, based on the matrix-vector pseudo noise generators.

摘要翻译： 本发明解决了以任意的偏移延迟有效地产生伪噪声序列的问题。 基于矩阵矢量伪噪声发生器，使用了新的和改进的架构。

公开(公告)号：US20030220953A1

公开(公告)日：2003-11-27

申请号：US10147844

申请日：2002-05-17

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Rustin W. Allred

IPC分类号： G06F001/02

CPC分类号： G06F1/0307 ,  G06F1/035 ,  G06F2101/12

摘要： A digital signal system (30) for determining an approximate logarithm of a value of x having a base b. The system comprises circuitry (32) for storing x as a digital representation and circuitry for identifying a most significant digit (MSD) of the digital representation. Adjacent the most significant digit is located a set of bits in respective lesser significant bit locations. The system further comprises a table (36) for storing a set of predetermined logarithms having the base b, wherein each of the predetermined logarithms corresponds to a number in a set of numbers. The system further comprises circuitry for addressing the table in response to a first bit group (t) of the set of bits in respective lesser significant bit locations, and in response the table is for outputting a one of the predetermined logarithms corresponding to a first number (Ia) in the set of numbers. Lastly, the system comprises circuitry (38) for outputting the approximate logarithm of the value of x in response to the one of the predetermined logarithms and further in response to a function estimation between logarithms at a first and second endpoint. The first endpoint corresponds to the first number in the set of numbers times a power of b and the second endpoint corresponds to a second number in the set of numbers times the power of b. Further, the function estimation estimates a logarithm at a number located at distance from one of the first and second endpoints, wherein the distance is responsive to a second bit group of the set of bits.

摘要翻译： 一种用于确定具有基底b的x的近似对数的数字信号系统（30）。 该系统包括用于存储x作为数字表示的电路（32）和用于识别数字表示的最高有效数字（MSD）的电路。 邻近最高有效位位于相应较低有效位位置的一组位。 该系统还包括一个用于存储一组具有基础b的预定对数的表（36），其中每个预定对数对应于一组数字中的一个数字。 系统还包括用于响应于相应较低有效位位置中的位组的第一位组（t）寻址表的电路，并且响应该表用于输出对应于第一数字的预定对数中的一个 （Ia）中的数字。 最后，该系统包括用于响应于预定对数中的一个输出x的值的近似对数并进一步响应于在第一和第二端点处的对数之间的函数估计的电路（38）。 第一个端点对应于一组数字中的第一个数字乘以b的幂，而第二个端点对应于数字集合中的第二个数乘以b的幂。 此外，功能估计估计位于距离第一和第二端点之一的距离处的数字上的对数，其中该距离响应该组位的第二位组。

公开(公告)号：US20030208516A1

公开(公告)日：2003-11-06

申请号：US10138688

申请日：2002-05-03

发明人： Jiening Ao ,  Thai-Bao H. Kien

IPC分类号： G06F001/02

CPC分类号： H03B29/00

摘要： The present invention is directed towards a low cost white noise generator. An oscillator provides a signal to an analog-to-digital (A/D) converter for digitizing. A bit-order reversal circuit reverses the order of the received bits, wherein the reversal circuit provides bits having an order ranging from LSB to MSB. A digital-to-analog (D/A) converter subsequently converts the reversed digital signal back to an analog signal, which is a white noise signal due to the random nature of reversing the bits provided by the A/D converter.

摘要翻译： 本发明涉及一种低成本白噪声发生器。 振荡器向模数转换器（A / D）转换器提供信号进行数字化处理。 位顺序反转电路反转接收位的顺序，其中反转电路提供具有从LSB到MSB的顺序的位。 数模（D / A）转换器随后将反转的数字信号转换回模拟信号，该模拟信号是由A / D转换器提供的位的反转的随机特性而产生的白噪声信号。

公开(公告)号：US20030154224A1

公开(公告)日：2003-08-14

申请号：US10012657

申请日：2001-10-30

发明人： Zhongnong Jiang ,  Rustin W. Allred

IPC分类号： G06F001/02 ,  G06F017/10

CPC分类号： H03H17/0607

摘要： Systems and methods for determining coefficients of an FIR filter are disclosed. The FIR filter coefficients are computed by determining a sine of an input value and an inverse of the input value. The sine of the input signal and the inverse of the input signal are multiplied together to form a sinc value of the input value. The sinc value is employed to determine the coefficient. The system and method can be repeated to compute any number of FIR filter coefficients in real-time. The sine of the input signal is computed utilizing a memory lookup table. The memory lookup table includes pairs of uniformly distributed values for the sine and cosine functions in the range of 0 to null. The inverse of the input value is computed using an inverse memory lookup table, a most significant digit and a remainder. The coefficient is then computed from a product of the sine of the input signal and the inverse of the input signal. Thus, the coefficient is computable in real-time without the use of previously computed and stored coefficients.

摘要翻译： 公开了用于确定FIR滤波器的系数的系统和方法。 通过确定输入值的正弦和输入值的倒数来计算FIR滤波器系数。 将输入信号的正弦和输入信号的反相相乘，形成输入值的sinc值。 采用sinc值来确定系数。 可以重复系统和方法来实时计算任意数量的FIR滤波器系数。 使用存储器查找表来计算输入信号的正弦。 存储器查找表包括在0到pi的范围内的正弦和余弦函数的均匀分布值对。 使用逆存储器查找表，最高有效数字和余数计算输入值的倒数。 然后根据输入信号的正弦和输入信号的反相的乘积计算系数。 因此，该系数可以实时计算，而不使用先前计算和存储的系数。