公开(公告)号：US20230171549A1

公开(公告)日：2023-06-01

申请号：US18059886

申请日：2022-11-29

Applicant: QUALCOMM Technologies, Inc.

Inventor： Michael CARFORE

IPC: H04R17/00 ,  B81B3/00

CPC classification number: H04R17/00 ,  B81B3/0051 ,  H04R2201/003 ,  B81B2201/0257

Abstract: Aspects of transducers with feedback transduction are described. One aspect is a transducer system comprising an operational amplifier having an inverting input, a non-inverting input, and an output. The transducer system also includes a piezoelectric microelectromechanical system (MEMS) transducer having a first node and a second node, wherein the first node is coupled to the inverting input of the operational amplifier, and wherein the piezoelectric MEMS transducer is configured to generate an electrical signal across the first node and the second node in response to a signal incident upon the piezoelectric MEMS transducer. The transducer system also includes an attenuator having an input and an output, wherein the input of the attenuator is coupled to the output of the operational amplifier, and wherein the output of the attenuator is coupled to the second node of the piezoelectric MEMS transducer.

公开(公告)号：US20230118025A1

公开(公告)日：2023-04-20

申请号：US17914297

申请日：2021-06-03

Applicant: QUALCOMM Technologies, Inc.

Inventor： Matthias REISSER ,  Max WELLING ,  Efstratios GAVVES ,  Christos LOUIZOS

IPC: G06N3/098 ,  G06N3/045

Abstract: A method of collaboratively training a neural network model, includes receiving a local update from a subset of the multiple users. The local update is related to one or more subsets of a dataset of the neural network model. A local component of the neural network model identifies a subset of the one or more subsets to which a data point belongs. A global update is computed for the neural network model based on the local updates from the subset of the users. The global updates for each portion of the network are aggregated to train the neural network model.

公开(公告)号：US11617048B2

公开(公告)日：2023-03-28

申请号：US16819673

申请日：2020-03-16

Applicant: Qualcomm Technologies Inc.

Inventor： Robert J. Littrell

IPC: H04R29/00 ,  G10L25/21 ,  G10L25/18 ,  H04R17/02 ,  G10L25/78 ,  H04R19/04

Abstract: An acoustic device is described and includes an acoustic sensor element configured to sense acoustic energy and produce an output signal and a threshold detector circuit including a switch having an input coupled to the output of the acoustic sensor element to receive the output signal, a control port that receives a control signal, and first and second output ports, a first channel including an analog-to-digital converter that operates at a first power level a second analog-to-digital converter that operates at a second higher power level, relative to the first power level and a threshold level detector that receives an output from the first analog-to-digital converter to produce the control signal having a first state that causes the switch feed the output signal from the acoustic sensor element to the second analog-to-digital converter when the first digitized output signal meets a threshold criteria.

公开(公告)号：US20230070439A1

公开(公告)日：2023-03-09

申请号：US17794555

申请日：2021-03-18

Applicant: QUALCOMM Technologies, Inc.

Inventor： Deepak Kumar GUPTA ,  Efstratios GAVVES ,  Arnold Wilhelmus Maria SMEULDERS

IPC: G06T7/73 ,  G06T5/20

Abstract: A method for object tracking includes receiving a target image of an object of interest. Latent space features of the target image is modified at a forward pass for a neural network by dropping at least one channel of the latent space features, dropping a channel corresponding to a slice of the latent space features, or dropping one or more features of the latent space features. At the forward pass, a location of the object of interest in a search image is predicted based on the modified latent space features. The location of the object of interest is identified by aggregating predicted locations from the forward pass.

公开(公告)号：US20230036702A1

公开(公告)日：2023-02-02

申请号：US17756957

申请日：2020-12-14

Applicant: Qualcomm Technologies, Inc.

Inventor： Matthias REISSER ,  Max WELLING ,  Efstratios GAVVES ,  Christos LOUIZOS

IPC: G06N3/02

Abstract: Aspects described herein provide a method of processing data, including: receiving a set of global parameters for a plurality of machine learning models; processing data stored locally on an processing device with the plurality of machine learning models according to the set of global parameters to generate a machine learning model output; receiving, at the processing device, user feedback regarding machine learning model output for the plurality of machine learning models; performing an optimization of the plurality of machine learning models based on the machine learning output and the user feedback to generate locally updated machine learning model parameters; sending the locally updated machine learning model parameters to a remote processing device; and receiving a set of globally updated machine learning model parameters for the plurality of machine learning models.

公开(公告)号：US11567746B2

公开(公告)日：2023-01-31

申请号：US16927016

申请日：2020-07-13

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Muthu M. Baskaran ,  Thomas Henretty ,  Richard A. Lethin ,  Benoit J. Meister

IPC: G06F8/41

Abstract: In a sequence of major computational steps or in an iterative computation, a stencil amplifier can increase the number of data elements accessed from one or more data structures in a single major step or iteration, thereby decreasing the total number of computations and/or communication operations in the overall sequence or the iterative computation. Stencil amplification, which can be optimized according to a specified parameter such as compile time, rune time, code size, etc., can improve the performance of a computing system executing the sequence or the iterative computation in terms of run time, memory load, energy consumption, etc. The stencil amplifier typically determines boundaries, to avoid erroneously accessing data elements not present in the one or more data structures.

公开(公告)号：US11537373B2

公开(公告)日：2022-12-27

申请号：US17034895

申请日：2020-09-28

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Muthu Manikandan Baskaran ,  Benoit J. Meister ,  Benoit Pradelle

IPC: G06F8/41

Abstract: A system for compiling programs for execution thereof using a hierarchical processing system having two or more levels of memory hierarchy can perform memory-level-specific optimizations, without exceeding a specified maximum compilation time. To this end, the compiler system employs a polyhedral model and limits the dimensions of a polyhedral program representation that is processed by the compiler at each level using a focalization operator that temporarily reduces one or more dimensions of the polyhedral representation. Semantic correctness is provided via a defocalization operator that can restore all polyhedral dimensions that had been temporarily removed.

公开(公告)号：US11500557B2

公开(公告)日：2022-11-15

申请号：US16745890

申请日：2020-01-17

Applicant: QUALCOMM TECHNOLOGIES, INC.

Inventor： Muthu M. Baskaran ,  Thomas Henretty ,  Ann Johnson ,  Athanasios Konstantinidis ,  M. H. Langston ,  Janice O. McMahon ,  Benoit J. Meister ,  Paul D. Mountcastle ,  Aale Naqvi ,  Benoit Pradelle ,  Tahina Ramananandro ,  Sanket Tavarageri ,  Richard A. Lethin

IPC: G06F9/44 ,  G06F3/06 ,  G06F8/41

Abstract: A compilation system using an energy model based on a set of generic and practical hardware and software parameters is presented. The model can represent the major trends in energy consumption spanning potential hardware configurations using only parameters available at compilation time. Experimental verification indicates that the model is nimble yet sufficiently precise, allowing efficient selection of one or more parameters of a target computing system so as to minimize power/energy consumption of a program while achieving other performance related goals. A voltage and/or frequency optimization and selection is presented which can determine an efficient dynamic hardware configuration schedule at compilation time. In various embodiments, the configuration schedule is chosen based on its predicted effect on energy consumption. A concurrency throttling technique based on the energy model can exploit the power-gating features exposed by the target computing system to increase the energy efficiency of programs.

公开(公告)号：US20220359338A1

公开(公告)日：2022-11-10

申请号：US17313412

申请日：2021-05-06

Applicant: QUALCOMM Technologies, Inc. ,  RF360 Europe GmbH

Inventor： Jose MOREIRA ,  Markus VALTERE ,  Bart KASSTEEN ,  Alberto Jose TEIXEIRA DE QUEIROS

IPC: H01L23/367 ,  H01L23/522 ,  H01L23/373 ,  H01L21/56 ,  H05K1/02

Abstract: Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer, where each of the plurality of heat sink interconnects is directly coupled to the heat transfer layer in a vertical orientation.

公开(公告)号：US20220359337A1

公开(公告)日：2022-11-10

申请号：US17313380

申请日：2021-05-06

Applicant: QUALCOMM Technologies, Inc. ,  RF360 Europe GmbH

Inventor： Jose MOREIRA ,  Markus VALTERE ,  Juergen PORTMANN ,  Jeroen BIELEN

IPC: H01L23/367 ,  H01L23/522 ,  H05K1/02 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56 ,  H03F3/213

Abstract: Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer. The plurality of heat sink interconnects is located adjacent the high-power die in a horizontal direction.