公开(公告)号：US20220344294A1

公开(公告)日：2022-10-27

申请号：US17236425

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Semiconductor devices having interconnect structures with vertically offset bonding surfaces, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate at least partially covered by a first dielectric material having an upper surface, and an interconnect structure extending therefrom. The interconnect structure can include a plurality of conductive elements, and a continuous region of a first insulating material at least partially between the plurality of conductive elements. The plurality of conductive elements and the continuous region can have coplanar end surfaces. The interconnect structure can further include a perimeter structure at least partially surrounding the plurality of conductive elements and the continuous region. The perimeter structure can have an uppermost surface that can be vertically offset from the upper surface of the first dielectric material and/or the coplanar end surfaces.

公开(公告)号：US20220336273A1

公开(公告)日：2022-10-20

申请号：US17850848

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/306 ,  H01L21/311

Abstract: Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

公开(公告)号：US11289440B1

公开(公告)日：2022-03-29

申请号：US17035579

申请日：2020-09-28

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Bret K. Street

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00

Abstract: Systems and methods for semiconductor devices having a substrate with bond pads, a die pair in a stacked configuration above the bond pads and having a first die having an oxide layer, a second die having an oxide layer attached to the first oxide layer, and conductive bonds electrically coupling the dies. Interconnects extend between the bond pads and the die pair, electrically coupling die pair to the substrate. The device may include a second die pair electrically coupled to: (1) the first die pair with secondary interconnects; and (2) the substrate with through-silicon vias extending through the first die pair. The top die of a die pair may be a thick die for use at the top of a pair stack. Pairs may be created by matching dies of a first silicon wafer to dies of a second silicon wafer, combination bonding the wafers, and dicing the die pairs.

公开(公告)号：US20210202411A1

公开(公告)日：2021-07-01

申请号：US17201874

申请日：2021-03-15

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

公开(公告)号：US20210134670A1

公开(公告)日：2021-05-06

申请号：US16671577

申请日：2019-11-01

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Owen R. Fay

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L21/463

Abstract: A method of coupling a first semiconductor device to a second semiconductor device can include encapsulating solder balls on a first surface of a first substrate of the first semiconductor device with an encapsulant material. In some embodiments, the method includes removing a portion of the encapsulant material and a portion the solder balls to form a mating surface. The method can include reflowing the solder balls. In some embodiments, the method includes inserting exposed conductive pillars of the second semiconductor device into the reflowed solder balls.

公开(公告)号：US10998271B1

公开(公告)日：2021-05-04

申请号：US16671558

申请日：2019-11-01

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Akshay N. Singh

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

Abstract: A semiconductor device assembly can include a semiconductor device having a substrate and vias electrically connected to circuitry of the semiconductor device. Individual vias can have an embedded portion extending from the first side to the second side of the substrate and an exposed portion projecting from the second side of the substrate. The assembly can include a density-conversion connector comprising a connector substrate and a first array of contacts formed at the first side thereof, the first array of contacts occupying a first footprint area on the first side thereof, and wherein individual contacts of the first array are electrically connected to the exposed portion of a corresponding via of the semiconductor device. The assembly can include a second array of contacts electrically connected to the first array, formed at the second side of the connector substrate, and occupying a second footprint area larger than the first footprint area.

公开(公告)号：US10978386B2

公开(公告)日：2021-04-13

申请号：US15133121

申请日：2016-04-19

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Philip J. Ireland ,  Sarah A. Niroumand

IPC: H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768

Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.

公开(公告)号：US10685878B2

公开(公告)日：2020-06-16

申请号：US14563953

申请日：2014-12-08

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/306 ,  H01L21/311

Abstract: Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

公开(公告)号：US20200066664A1

公开(公告)日：2020-02-27

申请号：US16667360

申请日：2019-10-29

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

公开(公告)号：US10483221B2

公开(公告)日：2019-11-19

申请号：US15797638

申请日：2017-10-30

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.