公开(公告)号：US20210311829A1

公开(公告)日：2021-10-07

申请号：US17348211

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Jongtae Kwak ,  Aaron P. Boehm

IPC: G06F11/10 ,  G11C7/10

Abstract: Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.

公开(公告)号：US20210294530A1

公开(公告)日：2021-09-23

申请号：US17180503

申请日：2021-02-19

Applicant: Micron Technology, Inc

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F3/06

Abstract: Methods, systems, and devices related to operating a memory array are described. A system may include a memory device and a host device. A memory device may indicate information about a temperature of the memory device, which may include sending an indication to the host device after receiving a signal that initializes the operation of the memory device or storing an indication, for example in a register, about the temperature of the memory device. The information may include an indication that a temperature of the memory device or a rate of change of the temperature of the memory device has satisfied a threshold. Operation of the memory device, or the host device, or both may be modified based on the information about the temperature of the memory device. Operational modifications may include delaying a sending or processing of memory commands until the threshold is satisfied.

公开(公告)号：US11061771B2

公开(公告)日：2021-07-13

申请号：US16803856

申请日：2020-02-27

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Jongtae Kwak ,  Aaron P. Boehm

IPC: G06F11/10 ,  G11C7/10

Abstract: Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.

公开(公告)号：US10983934B2

公开(公告)日：2021-04-20

申请号：US16931144

申请日：2020-07-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Matthew A. Prather

IPC: G11C5/14 ,  G06F13/16 ,  G06F5/06 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3206

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

公开(公告)号：US20210049068A1

公开(公告)日：2021-02-18

申请号：US16940783

申请日：2020-07-28

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F11/10 ,  H03M13/29

Abstract: Methods, systems, and devices for coordinated error correction are described. A memory device may indicate, for example to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. After performing the comparison, an indication of or based on whether the compared error correction codes match may be provided to the external device. The external device may use the indication to detect errors in the received version of the data, or to manage data storage in the memory device, or both, among other operations.

公开(公告)号：US20200349097A1

公开(公告)日：2020-11-05

申请号：US16931144

申请日：2020-07-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Matthew A. Prather

IPC: G06F13/16 ,  G06F1/3296 ,  G06F5/06 ,  G06F1/3206 ,  G06F1/3234

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

公开(公告)号：US20200258566A1

公开(公告)日：2020-08-13

申请号：US16786737

申请日：2020-02-10

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G11C11/406

Abstract: Methods, systems, and devices for refresh rate management for a memory device are described. A memory device may receive refresh commands for a memory array (e.g., from a host device). The memory device may determine that a refresh rate associated with the refresh commands is below a threshold, and the threshold may be based on a condition of the memory array. The memory device may transmit signaling (e.g., to a host device) indicating that the refresh rate associated with the refresh commands is below the threshold. Additionally or alternatively, the memory device may switch from a first mode of operation to a second mode of operation based on determining that the refresh rate associated with the refresh commands is below the threshold. The second mode of operation may restrict access to at least a portion of the memory array. Additionally or alternatively, the second mode of operation may include a self-refresh mode.