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公开(公告)号：US11336298B2
公开(公告)日：2022-05-17
申请号：US17170259
申请日：2021-02-08
发明人： Jongtae Kwak
摘要： Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).
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公开(公告)号：US10951232B2
公开(公告)日：2021-03-16
申请号：US16199773
申请日：2018-11-26
发明人： Jongtae Kwak
摘要： Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).
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公开(公告)号：US20200341841A1
公开(公告)日：2020-10-29
申请号：US16871329
申请日：2020-05-11
发明人： Jongtae Kwak
IPC分类号： G06F11/10 , G11C11/22 , G11C11/406 , G11C29/52 , G11C11/4076 , G11C11/4099
摘要： Methods, systems, and devices for an error correcting code scrub scheme are described. A memory device may correct an error associated with a first data bit or a first parity bit of a plurality of data bits and a plurality of parity bits, respectively. The memory device may correct the error by reading each of the plurality of data bits and the plurality of parity bits from a memory array, and determining that an error associated with a single bit exists. The memory device may then correct the determined single-bit error, and may write the corrected bit directly back to the memory array.
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公开(公告)号：US10691533B2
公开(公告)日：2020-06-23
申请号：US15839617
申请日：2017-12-12
发明人： Jongtae Kwak
IPC分类号： G06F11/00 , G06F11/10 , G11C11/22 , G11C11/406 , G11C29/52 , G11C11/4076 , G11C11/4099 , G11C7/10 , G11C29/04
摘要： Methods, systems, and devices for an error correcting code scrub scheme are described. A memory device may correct an error associated with a first data bit or a first parity bit of a plurality of data bits and a plurality of parity bits, respectively. The memory device may correct the error by reading each of the plurality of data bits and the plurality of parity bits from a memory array, and determining that an error associated with a single bit exists. The memory device may then correct the determined single-bit error, and may write the corrected bit directly back to the memory array.
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公开(公告)号：US09659631B2
公开(公告)日：2017-05-23
申请号：US14602084
申请日：2015-01-21
发明人： Onegyun Na , Jongtae Kwak , Seong-Hoon Lee , Hoon Choi
IPC分类号： G11C7/00 , G11C7/22 , G11C11/4091 , G11C7/06 , G11C7/02
CPC分类号： G11C11/4091 , G11C7/02 , G11C7/06 , G11C7/062 , G11C7/065 , G11C11/4074 , G11C2207/063 , G11C2207/2281
摘要： A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.
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6.发明申请APPARATUSES AND METHODS FOR CONTROLLING A CLOCK SIGNAL PROVIDED TO A CLOCK TREE 有权用于控制提供给时钟树的时钟信号的装置和方法公开(公告)号：US20150318032A1
公开(公告)日：2015-11-05
申请号：US14800512
申请日：2015-07-15
CPC分类号： G11C7/222 , G11C7/1057 , G11C7/1084 , G11C7/1087 , G11C7/109 , H03K19/0005
摘要： Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. The example apparatus further includes a clock signal control circuit coupled to the consecutive write command detection circuit and configured to control a clock signal to an input/output (I/O) latch based on whether the consecutive write command detection circuit detects that the next write command is within the consecutive write command period.
摘要翻译： 描述了用于控制时钟树的时钟信号的装置，感测电路和方法。 一种示例性装置包括一个连续的写入命令检测电路，其被配置为响应于在写入命令寄存器的输出处提供的当前写入命令来检测在当前写入命令的连续写入命令周期内是否接收到下一个写入命令。 该示例设备还包括一个时钟信号控制电路，该时钟信号控制电路耦合到该连续的写命令检测电路，并且被配置为基于该连续的写入命令检测电路是否检测到下一个写入来控制到输入/输出（I / O） 命令在连续写入命令周期内。
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公开(公告)号：US20140313837A1
公开(公告)日：2014-10-23
申请号：US13867544
申请日：2013-04-22
发明人： Jongtae Kwak
CPC分类号： G11C7/106 , G11C7/1018 , G11C7/1066 , G11C7/222
摘要： A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by using substantially the same latency delayed received command indications. A downstream clock generation circuit generates a clock signal from a received command indication delayed by both a delay locked loop and latency delays stored in latency control circuits. An upstream clock generation circuit generates a clock signal from the received command indication delayed by the delay locked loop and capture indications from the latency control circuits.
摘要翻译： 用于控制动态突发长度控制数据的存储器，系统和方法可以通过使用基本上相同的等待时间延迟的接收命令指示来为上游计数器和下游计数器产生时钟。 下行时钟产生电路从延迟锁定环路延迟的接收到的命令指示和等待时间控制电路中存储的等待时延延迟生成时钟信号。 上行时钟发生电路根据延迟锁定环延迟的接收命令指示产生时钟信号，并从等待时间控制电路捕获指示。
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公开(公告)号：US20220319581A1
公开(公告)日：2022-10-06
申请号：US17220110
申请日：2021-04-01
发明人： Yuan He , Jongtae Kwak
IPC分类号： G11C11/4094
摘要： Memory device data-access schemes are disclosed. Various embodiments may include a memory device including a first column plane, a second column plane, and a data-steering circuit. The first column plane may include a first edge, a second edge, and a first number of digit lines arranged between the first edge and the second edge. The second column plane may include a third edge positioned adjacent to the second edge, a fourth edge, and a second number of digit lines arranged between the third edge and the fourth edge. The data-steering circuit may be configured to logically relate a first digit line of the first number of digit lines to a second digit line of the second number of digit lines, the first digit line proximate to the first edge and the second digit line proximate to the fourth edge. Associated systems and methods are also disclosed.
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公开(公告)号：US20220247428A1
公开(公告)日：2022-08-04
申请号：US17726349
申请日：2022-04-21
发明人： Jongtae Kwak
摘要： Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).
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公开(公告)号：US20210383888A1
公开(公告)日：2021-12-09
申请号：US16895960
申请日：2020-06-08
摘要： Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.
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