公开(公告)号：US11671593B2

公开(公告)日：2023-06-06

申请号：US17488640

申请日：2021-09-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Takashi Hashimoto

IPC: H04N19/117 ,  H04N19/14 ,  H04N19/176 ,  H04N19/196

CPC classification number: H04N19/117 ,  H04N19/14 ,  H04N19/176 ,  H04N19/196

Abstract: An encoder includes processing circuitry and memory. Using the memory, the processing circuitry: encodes and reconstructs an image to generate a reconstructed image; determines, according to a characteristic of a block in the reconstructed image, an interpolation method for interpolating pixels located outside a referable region including the block; interpolates the pixels located outside the referable region, using the interpolation method determined; and applies a filter to the block using the pixels interpolated.

公开(公告)号：US11665370B2

公开(公告)日：2023-05-30

申请号：US17379302

申请日：2021-07-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/70 ,  H04N19/169 ,  H04N19/423 ,  H04N19/46

CPC classification number: H04N19/70 ,  H04N19/188 ,  H04N19/423 ,  H04N19/46

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: writes, into a sequence parameter set which is header information of a sequence, video usability information syntax which is information for realizing an additional function in display of an image, and syntax different from the video usability information syntax. The syntax includes at least one parameter related to display timing of the image.

公开(公告)号：US11616977B2

公开(公告)日：2023-03-28

申请号：US17473479

申请日：2021-09-13

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh

IPC: H04N19/537 ,  H04N19/105 ,  H04N19/157 ,  H04N19/52 ,  H04N19/573

Abstract: An encoder includes memory and circuitry. The circuitry: derives a first motion vector in a unit of a prediction block using a first inter frame prediction mode that uses a degree of matching between two reconstructed images of two regions in two difference pictures, the prediction block being obtained by splitting an image included in a video; and performs, in the unit of the prediction block, a first motion compensation process that generates a prediction image by referring to a spatial gradient of luminance in an image generated by performing motion compensation using the first motion vector derived.

公开(公告)号：US11593970B2

公开(公告)日：2023-02-28

申请号：US17365243

申请日：2021-07-01

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Toshiyasu Sugio ,  Takahiro Nishi ,  Tadamasa Toma ,  Toru Matsunobu ,  Satoshi Yoshikawa ,  Tatsuya Koyama

IPC: G06T9/40 ,  G06T17/00 ,  G06T9/00 ,  G06T15/08

Abstract: A three-dimensional data encoding method includes: extracting, from first three-dimensional data, second three-dimensional data having an amount of a feature greater than or equal to a threshold; and encoding the second three-dimensional data to generate first encoded three-dimensional data. For example, the three-dimensional data encoding method may further include encoding the first three-dimensional data to generate the second encoded three-dimensional data.

公开(公告)号：US11563958B2

公开(公告)日：2023-01-24

申请号：US17233804

申请日：2021-04-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/196 ,  H04N19/105 ,  H04N19/14 ,  H04N19/176 ,  H04N19/436

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: derives a correction parameter using only a neighboring reconstructed image that neighbors a processing unit which has a determined size and is located at an upper left of a current block to be processed in an image, among neighboring reconstructed images that neighbor the current block, and performs correction processing of the current block based on the correction parameter derived, when the current block has a size larger than the determined size.

公开(公告)号：US11528508B2

公开(公告)日：2022-12-13

申请号：US17589393

申请日：2022-01-31

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chu Tong Wang ,  Chong Soon Lim ,  Han Boon Teo ,  Hai Wei Sun ,  Jing Ya Li ,  Che-Wei Kuo ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/82 ,  H04N19/117 ,  H04N19/132 ,  H04N19/167 ,  H04N19/17 ,  H04N19/186

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in response to a first reconstructed image sample being located outside a virtual boundary, duplicates a reconstructed sample located inside and adjacent to the virtual boundary to generate the first reconstructed image sample. The circuitry generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to the first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value.

公开(公告)号：US11509908B2

公开(公告)日：2022-11-22

申请号：US16564680

申请日：2019-09-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe

IPC: H04N19/159 ,  H04N19/12 ,  H04N19/117 ,  H04N19/176 ,  H04N19/124 ,  H04N19/182

Abstract: An encoder includes circuitry and a memory connected to the circuitry. In operation, the circuitry: generates a plurality of predicted values of a pixel in a current picture to be encoded, using a plurality of reference pixels in the current picture, and enables or disables a process of determining a predicted value of the pixel on a block-by-block basis based on availability of at least one reference pixel among the plurality of reference pixels by filtering the plurality of predicted values based on a position of the pixel.

公开(公告)号：US11503318B2

公开(公告)日：2022-11-15

申请号：US17388694

申请日：2021-07-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Che-Wei Kuo ,  Chong Soon Lim ,  Han Boon Teo ,  Jing Ya Li ,  Hai Wei Sun ,  Chu Tong Wang ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/00 ,  H04N19/44 ,  H04N19/105 ,  H04N19/117 ,  H04N19/13 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186 ,  H04N19/46

Abstract: A decoder includes circuitry which, in operation, parses a first flag indicating whether a CCALF (cross component adaptive loop filtering) process is enabled for a first block located adjacent to a left side of a current block; parses a second flag indicating whether the CCALF process is enabled for a second block located adjacent to an upper side of the current block; determines a first index associated with a color component of the current block; and derives a second index indicating a context model, using the first flag, the second flag, and the first index. The circuitry, in operation, performs entropy decoding of a third flag indicating whether the CCALF process is enabled for the current block, using the context model indicated by the second index; and performs the CCALF process on the current block in response to the third flag indicating the CCALF process is enabled for the current block.

公开(公告)号：US11457240B2

公开(公告)日：2022-09-27

申请号：US16840906

申请日：2020-04-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Tadamasa Toma ,  Kiyofumi Abe ,  Takahiro Nishi ,  Masato Ohkawa ,  Hideo Saitou

IPC: H04N11/02 ,  H04N19/60 ,  H04N19/124 ,  H04N19/176 ,  H04N19/44

Abstract: An encoder which transforms a current block to be encoded in an image to encode the current block includes circuitry and memory. The circuitry, using the memory: determines a plurality of first transform basis candidates and transforms the current block using a transform basis included in the plurality of first transform basis candidates determined, when the current block has a first size; and determines one or more second transform basis candidates different from the plurality of first transform basis candidates and transforms the current block using a transform basis included in the one or more second transform basis candidates determined, when the current block has a second size larger than the first size.

公开(公告)号：US11457215B2

公开(公告)日：2022-09-27

申请号：US17034825

申请日：2020-09-28

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Ryuichi Kanoh ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/126 ,  H04N19/176 ,  H04N19/18

Abstract: Various embodiments provide an encoder that performs an up-conversion and a down-conversion on a first quantization matrix to generate a second quantization matrix, and quantizes transform coefficients of a current block using the second quantization matrix. The first quantization matrix has a first number of rows and a first number of columns equal to the first number of rows, and the second quantization matrix has a second number of rows and a second number of columns different from the second number of rows. In the up-conversion, the circuitry generates the second quantization matrix such that one of the second number of rows or the second number of columns is larger than the first number of rows. In the down-conversion, the circuitry generates the second quantization matrix such that the other of the second number of rows or the second number of columns is smaller than the first number of rows.