公开(公告)号：US06190959B1

公开(公告)日：2001-02-20

申请号：US09413435

申请日：1999-10-06

申请人： Gary Bela Bronner ,  Jack Allan Mandelman ,  Donald James Samuels

发明人： Gary Bela Bronner ,  Jack Allan Mandelman ,  Donald James Samuels

IPC分类号： H01L218242

CPC分类号： H01L27/1087

摘要： Disclosed herein is an arrangement of memory cells in which the spacing between back-to-back trench capacitors is defined at less than 1 F spacing. A pure phase edge mask is used to define such trench patterns having less than 1 F spacing. The reduction in the trench-to-trench spacing results in increased separation between the trench and the near edge of the gate conductor. This increase in the trench to gate conductor spacing, in turn, permits the channel doping concentration to be decreased, with a corresponding increase in ON current to be realized. In alternative embodiments, a pure phase edge mask or a blocked phase edge mask can be used to define trench patterns in which the width of trenches is increased to form storage capacitors having higher capacitance. In such embodiments, the spacing between back-to-back trenches can be reduced, such that the total separation between the outer edges of adjacent trenches is maintained at about 3 F or less.

摘要翻译： 本文公开了一种存储单元的布置，其中背对背沟槽电容器之间的间隔被限定在小于1F的间隔。 使用纯相边缘掩模来限定具有小于1F间距的这种沟槽图案。 沟槽间距的减小导致沟槽和栅极导体的近边缘之间的间隔增加。 沟槽与栅极导体间隔的增加又使得沟道掺杂浓度降低，同时实现ON电流的相应增加。 在替代实施例中，可以使用纯相边缘掩模或阻挡相边缘掩模来限定其中沟槽宽度增加以形成具有较高电容的存储电容器的沟槽图案。 在这样的实施例中，可以减小背对背沟槽之间的间隔，使得相邻沟槽的外边缘之间的总间隔保持在约3°F或更小。

公开(公告)号：US6110824A

公开(公告)日：2000-08-29

申请号：US816586

申请日：1997-03-13

申请人： Thomas John Licata ,  Jack Allan Mandelman

发明人： Thomas John Licata ,  Jack Allan Mandelman

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L21/461 ,  H01L21/4763 ,  H01L23/485

CPC分类号： H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002

摘要： Capacitive coupling, and attendant cross-talk, is reduced by increasing the distance between wire surfaces in integrated circuit applications. This is done by changing wire shape from the conventional rectangular cross-section. A cross-section which consists of a rectangular portion and a shaped, triangular portion is created, having the effect of increasing the effective distance between adjacent conductors. Cross-sectional area of wires is maintained and thus the current carrying capacity is maintained. The wire shapes may be produced using several alternate methods.

摘要翻译： 通过增加集成电路应用中电线表面之间的距离，减少了电容耦合和伴随的串扰。 这是通过从传统的矩形横截面改变线形而完成的。 产生由矩形部分和成形的三角形部分组成的横截面，其具有增加相邻导体之间的有效距离的作用。 导线的横截面面积得以维持，从而保持载流能力。 线形状可以使用几种替代方法制造。

公开(公告)号：US5994202A

公开(公告)日：1999-11-30

申请号：US788065

申请日：1997-01-23

申请人： Jeffrey Peter Gambino ,  Gary Bela Bronner ,  Jack Allan Mandelman ,  Larry Alan Nesbit

发明人： Jeffrey Peter Gambino ,  Gary Bela Bronner ,  Jack Allan Mandelman ,  Larry Alan Nesbit

IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/76

CPC分类号： H01L21/823412 ,  H01L21/76229 ,  H01L21/76237

摘要： A semiconductor MOSFET device is formed on a silicon substrate which includes trenches filled with Shallow Trench Isolation dielectric trench fill structures and extending above the surface of the substrate. The trench fill structures have protruding sidewalls with channel regions in the substrate having corner regions adjacent to the trench fill structures. The channel regions are between and adjacent to the STI trench fill structures doped with one concentration of dopant in the centers of the channel regions with a higher concentration of dopant in the corner regions. The dopant concentration differential provides a substantially equal concentration of electrons in the centers and at the corner regions of the channel regions.

摘要翻译： 半导体MOSFET器件形成在硅衬底上，该硅衬底包括填充有浅沟槽隔离电介质沟槽填充结构并在衬底表面上方延伸的沟槽。 沟槽填充结构具有突出的侧壁，其中衬底中的通道区域具有与沟槽填充结构相邻的拐角区域。 沟道区域在与沟槽区域的中心掺杂一个浓度的掺杂剂的STI沟槽填充结构之间并相邻，在拐角区域具有较高浓度的掺杂剂。 掺杂剂浓度差在通道区域的中心和拐角区域提供基本相等的电子浓度。