公开(公告)号：US6034877A

公开(公告)日：2000-03-07

申请号：US93902

申请日：1998-06-08

Applicant: Gary Bela Bronner ,  Jack Allan Mandelman ,  Donald James Samuels

Inventor： Gary Bela Bronner ,  Jack Allan Mandelman ,  Donald James Samuels

IPC: H01L21/8242 ,  G11C11/24

CPC classification number: H01L27/1087

Abstract: Disclosed herein is an arrangement of memory cells in which the spacing between back-to-back trench capacitors is defined at less than 1 F spacing. A pure phase edge mask is used to define such trench patterns having less than 1 F spacing. The reduction in the trench-to-trench spacing results in increased separation between the trench and the near edge of the gate conductor. This increase in the trench to gate conductor spacing, in turn, permits the channel doping concentration to be decreased, with a corresponding increase in ON current to be realized. In alternative embodiments, a pure phase edge mask or a blocked phase edge mask can be used to define trench patterns in which the width of trenches is increased to form storage capacitors having higher capacitance. In such embodiments, the spacing between back-to-back trenches can be reduced, such that the total separation between the outer edges of adjacent trenches is maintained at about 3 F or less.

Abstract translation: 本文公开了一种存储单元的布置，其中背对背沟槽电容器之间的间隔被限定在小于1F的间隔。 使用纯相边缘掩模来限定具有小于1F间距的这种沟槽图案。 沟槽间距的减小导致沟槽和栅极导体的近边缘之间的间隔增加。 沟槽与栅极导体间隔的增加又使得沟道掺杂浓度降低，同时实现ON电流的相应增加。 在替代实施例中，可以使用纯相边缘掩模或阻挡相边缘掩模来限定其中沟槽宽度增加以形成具有较高电容的存储电容器的沟槽图案。 在这样的实施例中，可以减小背对背沟槽之间的间隔，使得相邻沟槽的外边缘之间的总间隔保持在约3°F或更小。

公开(公告)号：US06190959B1

公开(公告)日：2001-02-20

申请号：US09413435

申请日：1999-10-06

Applicant: Gary Bela Bronner ,  Jack Allan Mandelman ,  Donald James Samuels

Inventor： Gary Bela Bronner ,  Jack Allan Mandelman ,  Donald James Samuels

IPC: H01L218242

CPC classification number: H01L27/1087

Abstract: Disclosed herein is an arrangement of memory cells in which the spacing between back-to-back trench capacitors is defined at less than 1 F spacing. A pure phase edge mask is used to define such trench patterns having less than 1 F spacing. The reduction in the trench-to-trench spacing results in increased separation between the trench and the near edge of the gate conductor. This increase in the trench to gate conductor spacing, in turn, permits the channel doping concentration to be decreased, with a corresponding increase in ON current to be realized. In alternative embodiments, a pure phase edge mask or a blocked phase edge mask can be used to define trench patterns in which the width of trenches is increased to form storage capacitors having higher capacitance. In such embodiments, the spacing between back-to-back trenches can be reduced, such that the total separation between the outer edges of adjacent trenches is maintained at about 3 F or less.

Abstract translation: 本文公开了一种存储单元的布置，其中背对背沟槽电容器之间的间隔被限定在小于1F的间隔。 使用纯相边缘掩模来限定具有小于1F间距的这种沟槽图案。 沟槽间距的减小导致沟槽和栅极导体的近边缘之间的间隔增加。 沟槽与栅极导体间隔的增加又使得沟道掺杂浓度降低，同时实现ON电流的相应增加。 在替代实施例中，可以使用纯相边缘掩模或阻挡相边缘掩模来限定其中沟槽宽度增加以形成具有较高电容的存储电容器的沟槽图案。 在这样的实施例中，可以减小背对背沟槽之间的间隔，使得相邻沟槽的外边缘之间的总间隔保持在约3°F或更小。

公开(公告)号：US5862058A

公开(公告)日：1999-01-19

申请号：US648745

申请日：1996-05-16

Applicant: Donald James Samuels ,  Matthew R. Wordeman

Inventor： Donald James Samuels ,  Matthew R. Wordeman

IPC: G03F1/36 ,  G03F7/20 ,  H01L21/027 ,  G06F17/50 ,  G06K9/03

CPC classification number: G03F7/70625 ,  G03F7/70441 ,  G03F1/36

Abstract: An optical proximity correction method and system are disclosed that allows for the correction of line width deviations caused by nonlinear lithography tools by calculating required chrome on glass line widths for a desired printed line. Line width correction is determined based only on the pitch of the line, defined as the width of the line and the distance to an adjacent line. Correction information is calculated from an aerial simulation and is then organized by pitch to provide a more efficient means of line correction.

Abstract translation: 公开了一种光学邻近校正方法和系统，其允许通过针对期望的印刷线计算玻璃线宽度上的所需铬，来校正由非线性光刻工具引起的线宽偏差。 线宽校正仅基于线的间距确定，定义为线的宽度和与相邻线的距离。 校正信息是从空中仿真计算出来的，然后通过俯仰来组织，以提供更有效的线路校正方法。