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    Threshold voltage tailoring of corner of MOSFET device
    1.
    发明授权
    Threshold voltage tailoring of corner of MOSFET device 有权
    MOSFET器件角的阈值电压调整

    公开(公告)号：US6084276A

    公开(公告)日：2000-07-04

    申请号：US337904

    申请日：1999-06-22

    申请人： Jeffrey Peter Gambino ,  Gary Bela Bronner ,  Jack Allan Mandelman ,  Larry Alan Nesbit

    发明人： Jeffrey Peter Gambino ,  Gary Bela Bronner ,  Jack Allan Mandelman ,  Larry Alan Nesbit

    IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/76 ,  H01L29/00

    CPC分类号： H01L21/823412 ,  H01L21/76229 ,  H01L21/76237

    摘要： A semiconductor MOSFET device is formed on a silicon substrate which includes trenches filled with Shallow Trench Isolation dielectric trench fill structures and extending above the surface of the substrate. The trench fill structures have protruding sidewalls with channel regions in the substrate having corner regions adjacent to the trench fill structures. The channel regions are between and adjacent to the STI trench fill structures doped with one concentration of dopant in the centers of the channel regions with a higher concentration of dopant in the corner regions. The dopant concentration differential provides a substantially equal concentration of electrons in the centers and at the corner regions of the channel regions.

    摘要翻译： 半导体MOSFET器件形成在硅衬底上，该衬底包括填充有浅沟槽隔离电介质沟槽填充结构并在衬底表面上方延伸的沟槽。 沟槽填充结构具有突出的侧壁，其中衬底中的通道区域具有与沟槽填充结构相邻的拐角区域。 沟道区域在与沟槽区域的中心掺杂一个浓度的掺杂剂的STI沟槽填充结构之间并相邻，在拐角区域具有较高浓度的掺杂剂。 掺杂剂浓度差在通道区域的中心和拐角区域提供基本相等的电子浓度。

    Threshold voltage tailoring of the corner of a MOSFET device
    2.
    发明授权
    Threshold voltage tailoring of the corner of a MOSFET device 失效
    MOSFET器件角的阈值电压调整

    公开(公告)号：US5994202A

    公开(公告)日：1999-11-30

    申请号：US788065

    申请日：1997-01-23

    申请人： Jeffrey Peter Gambino ,  Gary Bela Bronner ,  Jack Allan Mandelman ,  Larry Alan Nesbit

    发明人： Jeffrey Peter Gambino ,  Gary Bela Bronner ,  Jack Allan Mandelman ,  Larry Alan Nesbit

    IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/76

    CPC分类号： H01L21/823412 ,  H01L21/76229 ,  H01L21/76237

    摘要： A semiconductor MOSFET device is formed on a silicon substrate which includes trenches filled with Shallow Trench Isolation dielectric trench fill structures and extending above the surface of the substrate. The trench fill structures have protruding sidewalls with channel regions in the substrate having corner regions adjacent to the trench fill structures. The channel regions are between and adjacent to the STI trench fill structures doped with one concentration of dopant in the centers of the channel regions with a higher concentration of dopant in the corner regions. The dopant concentration differential provides a substantially equal concentration of electrons in the centers and at the corner regions of the channel regions.

    摘要翻译： 半导体MOSFET器件形成在硅衬底上，该硅衬底包括填充有浅沟槽隔离电介质沟槽填充结构并在衬底表面上方延伸的沟槽。 沟槽填充结构具有突出的侧壁，其中衬底中的通道区域具有与沟槽填充结构相邻的拐角区域。 沟道区域在与沟槽区域的中心掺杂一个浓度的掺杂剂的STI沟槽填充结构之间并相邻，在拐角区域具有较高浓度的掺杂剂。 掺杂剂浓度差在通道区域的中心和拐角区域提供基本相等的电子浓度。

    Semiconductor memory array having sublithographic spacing between adjacement trenches and method for making the same
    3.
    发明授权
    Semiconductor memory array having sublithographic spacing between adjacement trenches and method for making the same 失效
    具有辅助沟槽之间的亚光刻间隔的半导体存储器阵列及其制造方法

    公开(公告)号：US6034877A

    公开(公告)日：2000-03-07

    申请号：US93902

    申请日：1998-06-08

    申请人： Gary Bela Bronner ,  Jack Allan Mandelman ,  Donald James Samuels

    发明人： Gary Bela Bronner ,  Jack Allan Mandelman ,  Donald James Samuels

    IPC分类号： H01L21/8242 ,  G11C11/24

    CPC分类号： H01L27/1087

    摘要： Disclosed herein is an arrangement of memory cells in which the spacing between back-to-back trench capacitors is defined at less than 1 F spacing. A pure phase edge mask is used to define such trench patterns having less than 1 F spacing. The reduction in the trench-to-trench spacing results in increased separation between the trench and the near edge of the gate conductor. This increase in the trench to gate conductor spacing, in turn, permits the channel doping concentration to be decreased, with a corresponding increase in ON current to be realized. In alternative embodiments, a pure phase edge mask or a blocked phase edge mask can be used to define trench patterns in which the width of trenches is increased to form storage capacitors having higher capacitance. In such embodiments, the spacing between back-to-back trenches can be reduced, such that the total separation between the outer edges of adjacent trenches is maintained at about 3 F or less.

    摘要翻译： 本文公开了一种存储单元的布置，其中背对背沟槽电容器之间的间隔被限定在小于1F的间隔。 使用纯相边缘掩模来限定具有小于1F间距的这种沟槽图案。 沟槽间距的减小导致沟槽和栅极导体的近边缘之间的间隔增加。 沟槽与栅极导体间隔的增加又使得沟道掺杂浓度降低，同时实现ON电流的相应增加。 在替代实施例中，可以使用纯相边缘掩模或阻挡相边缘掩模来限定其中沟槽宽度增加以形成具有较高电容的存储电容器的沟槽图案。 在这样的实施例中，可以减小背对背沟槽之间的间隔，使得相邻沟槽的外边缘之间的总间隔保持在约3°F或更小。

    Semiconductor memory array having sublithographic spacing between adjacent trenches and method for making the same
    4.
    发明授权
    Semiconductor memory array having sublithographic spacing between adjacent trenches and method for making the same 失效
    具有相邻沟槽之间的亚光刻间隔的半导体存储器阵列及其制造方法

    公开(公告)号：US06190959B1

    公开(公告)日：2001-02-20

    申请号：US09413435

    申请日：1999-10-06

    申请人： Gary Bela Bronner ,  Jack Allan Mandelman ,  Donald James Samuels

    发明人： Gary Bela Bronner ,  Jack Allan Mandelman ,  Donald James Samuels

    IPC分类号： H01L218242

    CPC分类号： H01L27/1087

    摘要： Disclosed herein is an arrangement of memory cells in which the spacing between back-to-back trench capacitors is defined at less than 1 F spacing. A pure phase edge mask is used to define such trench patterns having less than 1 F spacing. The reduction in the trench-to-trench spacing results in increased separation between the trench and the near edge of the gate conductor. This increase in the trench to gate conductor spacing, in turn, permits the channel doping concentration to be decreased, with a corresponding increase in ON current to be realized. In alternative embodiments, a pure phase edge mask or a blocked phase edge mask can be used to define trench patterns in which the width of trenches is increased to form storage capacitors having higher capacitance. In such embodiments, the spacing between back-to-back trenches can be reduced, such that the total separation between the outer edges of adjacent trenches is maintained at about 3 F or less.

    摘要翻译： 本文公开了一种存储单元的布置，其中背对背沟槽电容器之间的间隔被限定在小于1F的间隔。 使用纯相边缘掩模来限定具有小于1F间距的这种沟槽图案。 沟槽间距的减小导致沟槽和栅极导体的近边缘之间的间隔增加。 沟槽与栅极导体间隔的增加又使得沟道掺杂浓度降低，同时实现ON电流的相应增加。 在替代实施例中，可以使用纯相边缘掩模或阻挡相边缘掩模来限定其中沟槽宽度增加以形成具有较高电容的存储电容器的沟槽图案。 在这样的实施例中，可以减小背对背沟槽之间的间隔，使得相邻沟槽的外边缘之间的总间隔保持在约3°F或更小。

    Methods to prevent divot formation in shallow trench isolation areas
    8.
    发明授权
    Methods to prevent divot formation in shallow trench isolation areas 失效
    防止浅沟槽隔离区形成洞穴的方法

    公开(公告)号：US5923991A

    公开(公告)日：1999-07-13

    申请号：US740907

    申请日：1996-11-05

    申请人： Gary Bela Bronner ,  Jeffrey Peter Gambino ,  Larry A. Nesbit

    发明人： Gary Bela Bronner ,  Jeffrey Peter Gambino ,  Larry A. Nesbit

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76224

    摘要： A number of methods to prevent divot formation, and the resulting enhanced electric field associated therewith, are disclosed. In a first embodiment of the present invention, spacers having a low etch rate in hydrofluoric acid solution, and that can be etched selectively to silicon dioxide are used to protect the silicon nitride liner from forming the divot. In a second embodiment of the present invention, a silicon dioxide spacer is used prior to the etching of the trenches, to allow the formation of the divots above the level of the silicon wafer, where they are not problematic. In a third embodiment of the present invention, a multi layer polish stop is used to prevent the formation of the divot.

    摘要翻译： 公开了一些防止图形形成的方法以及与之相关的增强的电场。 在本发明的第一实施方案中，使用在氢氟酸溶液中具有低蚀刻速率且可被选择性地蚀刻到二氧化硅上的间隔物，以保护氮化硅衬垫免于形成裂缝。 在本发明的第二实施例中，在蚀刻沟槽之前使用二氧化硅间隔物，以允许在硅晶片的水平面之上形成凸点，这在它们没有问题。 在本发明的第三实施例中，使用多层抛光止挡件来防止形成凹陷。

    Resistance memory cell
    10.
    发明授权
    Resistance memory cell 有权
    电阻记忆单元

    公开(公告)号：US09305644B2

    公开(公告)日：2016-04-05

    申请号：US14125913

    申请日：2012-06-22

    申请人： Mark D. Kellam ,  Gary Bela Bronner

    发明人： Mark D. Kellam ,  Gary Bela Bronner

    IPC分类号： G11C13/00 ,  H01L45/00 ,  H01L27/24

    CPC分类号： G11C13/004 ,  G11C13/00 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0052 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2418 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143

    摘要： A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low-resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell.

    摘要翻译： 电阻存储器包括具有电阻存储元件和串联的两端存取装置的电阻存储单元。 双端子存取装置影响电阻存储单元的电流 - 电压特性。 电阻存储器还包括电路，跨越电阻存储单元施加具有设定极性的设定脉冲，以将电阻存储单元设置为在施加设置脉冲之后保持的低电阻状态，具有复位极性的复位脉冲 与设定的极性相反，将电阻存储单元复位到施加复位脉冲之后保持的高电阻状态，以及复位极性的读取脉冲和幅度比复位脉冲更小以确定电阻状态 的电阻存储单元，而不改变电阻存储单元的电阻状态。