公开(公告)号：US20240008247A1

公开(公告)日：2024-01-04

申请号：US17940577

申请日：2022-09-08

申请人： Changxin Memory Technologies, Inc.

发明人： Xiaojie LI

IPC分类号： H01L27/108 ,  G11C5/06

CPC分类号： H01L27/1087 ,  H01L27/10891 ,  H01L27/10885 ,  H01L27/10838 ,  H01L27/10876 ,  G11C5/063

摘要： The semiconductor structure forming method includes: providing a base, where the base includes a substrate, a plurality of first semiconductor layers and second semiconductor layers; forming a first sidewall and a second sidewall, each including a support layer and an isolation layer formed on a side of the support layer; forming a plurality of recessed portions separated by the first sidewall, the second sidewall, and the second semiconductor layers, where the recessed portions extend in a horizontal direction and are stacked in a vertical direction; forming a first conductive layer and a filling layer in each recessed portion; removing isolation layers located on a side of the first sidewall that is away from the second sidewall and on a side of the second sidewall that is away from the first sidewall; and removing the first conductive layer located at a bottom of each recessed portion.

公开(公告)号：US20230422466A1

公开(公告)日：2023-12-28

申请号：US17901853

申请日：2022-09-02

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Deyuan XIAO ,  Guangsu SHAO

IPC分类号： H01L27/108

CPC分类号： H01L27/1087 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10876

摘要： Embodiments relate to a semiconductor structure and a formation method thereof. The method for forming a semiconductor structure includes: forming a substrate and a semiconductor layer positioned above the substrate, where the semiconductor layer includes first trenches spaced along a first direction, the first direction being a direction parallel to a top surface of the substrate; forming, in the semiconductor layer, an isolation trench positioned below the first trenches, where the isolation trench extends along the first direction and continuously communicates with the first trenches; forming a first spacer at least positioned in the isolation trench; and forming a capacitor above the first spacer. The semiconductor structure and the formation method thereof reduce electric leakage between the substrate and the capacitor, thereby improving electrical performance of the semiconductor structure.

公开(公告)号：US20230209810A1

公开(公告)日：2023-06-29

申请号：US18046088

申请日：2022-10-12

申请人： Micron Technology, Inc.

发明人： Alyssa N. Scarbrough ,  David Ross Economy ,  John D. Hopkins ,  Jordan D. Greenlee ,  Mithun Kumar Ramasahayam

IPC分类号： H01L27/108 ,  H01L21/768

CPC分类号： H01L27/10885 ,  H01L21/7682 ,  H01L27/1087 ,  H01L21/76837

摘要： Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes an electrically insulating material and bit lines including copper in the electrically insulating material. The electrically insulating material defines air gaps between the bit lines. A method of manufacturing a memory device includes forming trenches in an electrically insulating material on or in circuitry of the memory device, forming a first electrically conductive material in the trenches, removing portions of the electrically insulating material to form air gaps between the trenches, recessing the first electrically conductive material, and replacing the first electrically conductive material that was removed with a second electrically conductive material. The second electrically conductive material is more electrically conductive than the first electrically conductive material. A memory device includes the apparatus. A computing system includes the memory device.

公开(公告)号：US20190067291A1

公开(公告)日：2019-02-28

申请号：US16111480

申请日：2018-08-24

申请人： STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

发明人： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL ,  Quentin HUBERT ,  Thomas CABOUT

IPC分类号： H01L27/108 ,  H01L29/66 ,  H01L49/02

CPC分类号： H01L27/10841 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/10876 ,  H01L28/60 ,  H01L29/66181 ,  H01L29/945

摘要： A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

公开(公告)号：US09960184B2

公开(公告)日：2018-05-01

申请号：US15645686

申请日：2017-07-10

申请人： GLOBALFOUNDRIES Inc.

发明人： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC分类号： H01L27/12 ,  H01L29/94 ,  H01L27/06 ,  H01L21/762 ,  H01L21/84 ,  H01L29/786 ,  H01L49/02 ,  H01L29/06 ,  H01L21/265 ,  H01L21/285 ,  H01L27/108

CPC分类号： H01L27/1207 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10829 ,  H01L27/1085 ,  H01L27/1087 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/786 ,  H01L29/94

摘要： A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.

公开(公告)号：US09881925B2

公开(公告)日：2018-01-30

申请号：US15192121

申请日：2016-06-24

申请人： International Business Machines Corporation

发明人： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC分类号： H01L27/108 ,  H01L29/06

CPC分类号： H01L27/10829 ,  H01L27/10826 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/10879 ,  H01L29/0649

摘要： A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a bonding layer in contact with a top surface of the substrate. At least one transistor contacts the bonding layer. The transistor includes at least one gate structure disposed on and in contact with a bottom surface of a semiconductor layer of the transistor. The semiconductor further includes a capacitor disposed adjacent to the transistor. The capacitor contacts the semiconductor layer of the transistor and extends down into the substrate. The method includes forming at least one transistor and then flipping the transistor. After the transistor has been flipped, the transistor is bonded to a new substrate. An initial substrate of the transistor is removed to expose a semiconductor layer. A capacitor is formed adjacent to the transistor and contacts with the semiconductor layer. A contact node is formed adjacent to the capacitor.

公开(公告)号：US20170365606A1

公开(公告)日：2017-12-21

申请号：US15691182

申请日：2017-08-30

申请人： International Business Machines Corporation

发明人： Michael V. Aquilino ,  Veeraraghavan S. Basker ,  Kangguo Cheng ,  Gregory Costrini ,  Ali Khakifirooz ,  Byeong Y. Kim ,  William L. Nicoll ,  Ravikumar Ramachandran ,  Reinaldo A. Vega ,  Hanfei Wang ,  Xinhui Wang

IPC分类号： H01L27/108 ,  H01L27/12

CPC分类号： H01L27/1087 ,  H01L27/0817 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/10879 ,  H01L27/1203

摘要： After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.

公开(公告)号：US09842830B1

公开(公告)日：2017-12-12

申请号：US15626534

申请日：2017-06-19

申请人： Darryl G. Walker

发明人： Darryl G. Walker

IPC分类号： G11C16/04 ,  G11C11/4074 ,  H01L25/065

CPC分类号： H01L25/0657 ,  G11C5/025 ,  G11C5/10 ,  G11C5/147 ,  G11C11/4063 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4099 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L27/1087 ,  H01L28/40 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/1436 ,  H01L2924/15311

摘要： A package can include first and second semiconductor devices stacked in a first direction. The first semiconductor device can include a first circuit formed on the first semiconductor device that provides a first potential greater than a ground potential at a first circuit output, and a second circuit coupled to receive the first circuit output. The second semiconductor device can include a first through via providing a first electrical connection between a first side and a second side of the second semiconductor device, and a third circuit. The first circuit output can be electrically connected to the first through via at the first side of the first semiconductor device and the third circuit can be electrically connected to the first through via at the second side of the first semiconductor device to receive the first potential.

公开(公告)号：US20170256709A1

公开(公告)日：2017-09-07

申请号：US15598605

申请日：2017-05-18

申请人： Samsung Electronics Co., Ltd.

发明人： Jongchul PARK ,  Hyungjoon KWON ,  lnho KIM ,  Jongsoon PARK

IPC分类号： H01L43/12 ,  H01L21/3213

CPC分类号： H01L43/12 ,  H01L21/32131 ,  H01L27/1087 ,  H01L27/222 ,  H01L43/08

摘要： A patterning method includes forming an etch-target layer on a substrate, forming mask patterns on the etch-target layer, and etching the etch-target layer using the mask patterns as an etch mask to form patterns spaced apart from each other. The etching process of the etch-target layer includes irradiating the etch-target layer with an ion beam, whose incident energy ranges from 600 eV to 10 keV. A recess region is formed in the etch-target layer between the mask patterns, and the ion beam is incident onto a bottom surface of the recess region at a first angle with respect to a top surface of the substrate and is incident onto an inner side surface of the recess region at a second angle with respect to the inner side surface of the recess region. The first angle ranges from 50° to 90° and the second angle ranges from 0° to 40°.

公开(公告)号：US20170250073A1

公开(公告)日：2017-08-31

申请号：US15595503

申请日：2017-05-15

申请人： International Business Machines Corporation

发明人： Takashi Ando ,  Eduard A. Cartier ,  Michael P. Chudzik ,  Aritra Dasgupta ,  Herbert L. Ho ,  Donghun Kang ,  Rishikesh Krishnan ,  Vijay Narayanan ,  Kern Rim

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01G4/005 ,  H01L21/322

CPC分类号： H01L21/02365 ,  H01G4/005 ,  H01L21/02178 ,  H01L21/02617 ,  H01L21/20 ,  H01L21/3221 ,  H01L23/26 ,  H01L27/10861 ,  H01L27/1087 ,  H01L28/60 ,  H01L28/90 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.