公开(公告)号：US20140022007A1

公开(公告)日：2014-01-23

申请号：US13945978

申请日：2013-07-19

Applicant: Analog Devices Technology

Inventor： Linus Sheng ,  Christopher W. Mangelsdorf

IPC: G05F3/02

CPC classification number: G05F3/02 ,  H02M3/07 ,  H02M2003/075

Abstract: An apparatus for transferring charge has a first charge pump path with a plurality of stages having first capacitors, and a second charge pump path, also with a plurality of stage having second capacitors, in parallel with the first charge pump path. The first and second charge pump paths are coupled to share a common output node. The apparatus also has a timing circuit coupled with the first and second charge pump paths. Among other things, the timing circuit is configured to cause at least one of the first capacitors to periodically charge at least one of the second capacitors.

Abstract translation: 一种用于传送电荷的装置具有第一电荷泵路径，其具有多个阶段，该第一电荷泵路径具有第一电容器，第二电荷泵路径也具有与第一电荷泵路径并联的具有第二电容器的多个级。 第一和第二电荷泵路径被耦合以共享公共输出节点。 该装置还具有与第一和第二电荷泵路径耦合的定时电路。 其中，定时电路被配置为使得第一电容器中的至少一个周期性地对第二电容器中的至少一个充电。

公开(公告)号：US20130342551A1

公开(公告)日：2013-12-26

申请号：US13892531

申请日：2013-05-13

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Boris Lerner ,  Michael Meyer-Pundsack ,  Gopal Gudhur Karanam ,  Pradip Thaker

IPC: G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

公开(公告)号：US20130249923A1

公开(公告)日：2013-09-26

申请号：US13892508

申请日：2013-05-13

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Michael Meyer-Pundsack ,  Boris Lerner ,  Gopal Gudhur Karanam ,  Pradip Thacker

IPC: G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract translation: 本发明的实施例提供了二维图像处理中的改进的定时控制，以便即使当处理操作转换到新的像素或新的像素帧时，仍然保持恒定的存储器读取速率和像素输出。 保持输入像素速率和输出像素速率之间的一对一关系，而不需要额外的时钟周期或存储器带宽，因为根据本发明的改进的定时控制通过预取一个新的像素数据列来利用空闲存储器带宽 在下一行或帧的第一像素块中，而当前行上的边缘像素块的新列被复制或清零。 当处理当前行上的边缘像素块时，下一行或帧的第一像素块中的数据就可以在没有额外的时钟周期或额外的存储器带宽的情况下进行计算。

公开(公告)号：US20130207821A1

公开(公告)日：2013-08-15

申请号：US13757455

申请日：2013-02-01

Applicant: Adrian W. SHERRY ,  Gabriel BANARIE ,  Roberto S. MAURINO

Inventor： Adrian W. SHERRY ,  Gabriel BANARIE ,  Roberto S. MAURINO

IPC: H03M3/00

CPC classification number: H03M3/30 ,  G06G7/184 ,  H03M3/322 ,  H03M3/358 ,  H03M3/458 ,  H03M3/496

Abstract: An integrator system may have a pair of sampling circuits each having a sampling capacitor to sample a respective component of a differential input signal, and an integrator having inputs coupled to outputs of the sampling circuits. The system may have a shorting switch coupled between input terminals of the sampling capacitors. The shorting switch may be engaged during an interstitial phase between sampling and output phases of the sampling circuits. By shorting input terminals of the sampling capacitors together, the design reduces current drawn by the system and, in some designs, severs relationships between current draw and information content sampled by the system. Configurations are disclosed for analog and digital input signals.

Abstract translation: 积分器系统可以具有一对采样电路，每个采样电路各自具有采样电容器以对差分输入信号的相应分量进行采样，以及具有耦合到采样电路的输出的输入的积分器。 该系统可以具有耦合在采样电容器的输入端之间的短路开关。 在采样电路的采样和输出阶段之间的间隙阶段，短路开关可能被接合。 通过将采样电容器的输入端子短路在一起，该设计减少了系统吸收的电流，并且在一些设计中，切断了电流抽取与系统采样的信息内容之间的关系。 公开了用于模拟和数字输入信号的配置。