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171.
公开(公告)号:US10992316B2
公开(公告)日:2021-04-27
申请号:US16390316
申请日:2019-04-22
Inventor: Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
IPC: G06F11/00 , H03M13/00 , H03M13/11 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/15 , G06T7/162 , H04W72/04
Abstract: A zero padding apparatus and method for fixed length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.
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公开(公告)号:US10979074B2
公开(公告)日:2021-04-13
申请号:US16559329
申请日:2019-09-03
Inventor: Sung-Ik Park , Heung-Mook Kim , Sun-Hyoung Kwon , Nam-Ho Hur
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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公开(公告)号:US10944434B2
公开(公告)日:2021-03-09
申请号:US16530758
申请日:2019-08-02
Inventor: Sung-Ik Park , Sun-Hyoung Kwon , Bo-Mi Lim , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
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174.
公开(公告)号:US10917276B2
公开(公告)日:2021-02-09
申请号:US16518058
申请日:2019-07-22
Inventor: Sung-Ik Park , Jae-Young Lee , Sun-Hyoung Kwon , Heung-Mook Kim
Abstract: An apparatus and method for broadcast signal frame using a bootstrap and a preamble are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.
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公开(公告)号:US10826537B2
公开(公告)日:2020-11-03
申请号:US16400988
申请日:2019-05-01
Inventor: Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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公开(公告)号:US10819373B2
公开(公告)日:2020-10-27
申请号:US16548189
申请日:2019-08-22
Inventor: Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.
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公开(公告)号:US10812864B2
公开(公告)日:2020-10-20
申请号:US16658283
申请日:2019-10-21
Inventor: Sung-Ik Park , Jae-Young Lee , Sun-Hyoung Kwon , Heung-Mook Kim
IPC: H04N21/61 , H04L1/00 , H04H20/42 , H04L5/00 , H04L27/36 , H04N21/2383 , H04L27/18 , H04L27/38 , H04W28/06
Abstract: An apparatus and method for broadcast signal frame using a bootstrap including a symbol for signaling a BICM mode and OFDM parameters of a preamble, together are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal. In this case, the bootstrap includes a symbol for signaling a BICM mode and OFDM parameters of L1-Basic of the preamble, together.
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178.
公开(公告)号:US10812104B2
公开(公告)日:2020-10-20
申请号:US16353378
申请日:2019-03-14
Inventor: Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
Abstract: A parity puncturing apparatus and method for fixed length signaling information are disclosed. A parity puncturing apparatus according to an embodiment of the present invention includes memory configured to provide a parity bit string for parity puncturing for the parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, and a processor configured to puncture a number of bits corresponding to a final puncturing size from the rear side of the parity bit string.
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公开(公告)号:US10778489B2
公开(公告)日:2020-09-15
申请号:US16520819
申请日:2019-07-24
Inventor: Sung-Ik Park , Jae-Young Lee , Sun-Hyoung Kwon , Heung-Mook Kim
Abstract: An apparatus and method for generating a broadcast signal frame including preamble for signaling injection level information. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes an injection level controller configured to generate a power reduced enhanced layer signal by reducing a power of an enhanced layer signal; a combiner configured to generate a multiplexed signal by combining a core layer signal and the power reduced enhanced layer signal; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling injection level information corresponding to the injection level controller.
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公开(公告)号:US10778254B2
公开(公告)日:2020-09-15
申请号:US16363778
申请日:2019-03-25
Inventor: Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
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