公开(公告)号：US11284394B2

公开(公告)日：2022-03-22

申请号：US16893740

申请日：2020-06-05

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04W72/04 ,  H04W72/08 ,  H04B10/2575 ,  H04W88/08 ,  H04L67/12

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (BBU) and remote radio heads (RRH). For example, a computing system including a BBU and a RRH may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the BBU and the RRH. The computing system may allocate the respective processing units to perform wireless processing stages associated with a wireless protocol. The BBU and/or the RRH may generate an output data stream based on the mixing of coefficient data with input data at the BBU and/or the RRH. Examples of systems and methods described herein may facilitate the processing of data for 5G (e.g., New Radio (NR)) wireless communications in a power-efficient and time-efficient manner.

公开(公告)号：US11159188B2

公开(公告)日：2021-10-26

申请号：US16432766

申请日：2019-06-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jeremy Chritz ,  Jaime Cummins ,  Tamara Schmitz

IPC: H04B1/04 ,  H04L1/00 ,  H03M13/15 ,  H04L5/14 ,  H04L5/00 ,  H04B1/12 ,  H04B1/525

Abstract: Examples described herein include methods, devices, and systems which may compensate input data for non-linear power amplifier noise to generate compensated input data. In compensating the noise, during an uplink transmission time interval (TTI), a switch path is activated to provide amplified input data to a receiver stage including a coefficient calculator. The coefficient calculator may calculate an error representative of the noise based partly on the input signal to be transmitted and a feedback signal to generate coefficient data associated with the power amplifier noise. The feedback signal is provided, after processing through the receiver, to a coefficient calculator. During an uplink TTI, the amplified input data may also be transmitted as the RF wireless transmission via an RF antenna. During a downlink TTI, the switch path may be deactivated and the receiver stage may receive an additional RF wireless transmission to be processed in the receiver stage.

公开(公告)号：US20210320678A1

公开(公告)日：2021-10-14

申请号：US16848514

申请日：2020-04-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo

IPC: H04B1/10 ,  H04B7/0413 ,  G06N3/04

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of multiple frequency bands transmission with a recurrent neural network that compensates for the self-interference noise generated by power amplifiers at harmonic frequencies of a respective wireless receiver. The recurrent neural network may be coupled to antennas of a wireless device and configured to generate the adjusted signals that compensate self-interference. The recurrent neural network may include a network of processing elements configured to combine transmission signals into sets of intermediate results. Each set of intermediate results may be summed in the recurrent neural network to generate a corresponding adjusted signal. The adjusted signal is receivable by a corresponding wireless receiver to compensate for the self-interference noise generated by a wireless transmitter transmitting on the same or different frequency band as the wireless receiver is receiving.

公开(公告)号：US11139845B2

公开(公告)日：2021-10-05

申请号：US16935699

申请日：2020-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04B1/62 ,  H04B1/04 ,  H04L25/03 ,  H04L1/00

Abstract: Systems, methods, and apparatuses for wireless communication are described. Input data for in-phase branch/quadrature branch (I/Q) imbalance or mismatch may be compensated for or non-linear power amplifier noise may be used to generate compensated input data. In some examples, a transmitter may be configured to transmit communications signaling via a first antenna, the transmitter including a filter configured for digital mismatch correction; a receiver may be configured to receive communications signaling via a second antenna; and a switch may be configured to selectively activate a first switch path to couple the transmitter and the first antenna and a second switch path to couple the receiver and the transmitter to provide communications signaling received via the transmitter as feedback for the filter through the receiver.

公开(公告)号：US20210149984A1

公开(公告)日：2021-05-20

申请号：US16689981

申请日：2019-11-20

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo

IPC: G06F17/16 ,  G06F17/14 ,  G06F1/03 ,  G06F12/02 ,  G11C11/4094

Abstract: Methods and apparatus for performing video processing matrix operations within a memory fabric. Various embodiments of the present disclosure are directed to converting a memory array into a matrix fabric for discrete cosine transform (DCT) matrix transformations and performing DCT matrix operations therein. Exemplary embodiments described herein perform DCT matrix-matrix multiplication operations within a memory device that includes a matrix fabric and matrix multiplication unit (MMU). In one embodiment, matrix-matrix multiplication operations are obtained using separate matrix-vector products. In one exemplary embodiment, the matrix fabric uses a “crossbar” construction of resistive elements. Each resistive element stores a level of impedance that represents the corresponding matrix coefficient value. The crossbar connectivity can be driven with an electrical signal representing the input vector as an analog voltage. The resulting signals can be converted from analog voltages to a digital values by an MMU to yield a vector-matrix product. In some cases, the MMU may additionally perform various other logical operations within the digital domain.

公开(公告)号：US20210143840A1

公开(公告)日：2021-05-13

申请号：US16683217

申请日：2019-11-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo

IPC: H03M13/15 ,  H03M13/11 ,  G06F7/544 ,  G06N3/04

Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to decode encoded data (e.g., data encoded using one or more encoding techniques). The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing the neural network decoders and/or recurrent neural networks. In this manner, neural networks or recurrent neural networks described herein may be used to implement error correction coding (ECC) decoders.

公开(公告)号：US10972139B1

公开(公告)日：2021-04-06

申请号：US16849696

申请日：2020-04-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo

IPC: H04B1/04 ,  H03F3/20 ,  G06N3/04

Abstract: Examples described herein include methods, devices, and systems which may compensate input data for nonlinear power amplifier noise to generate compensated input data. In compensating the noise, during an uplink transmission time interval (TTI), a switch path is activated to provide amplified input data to a receiver stage including a recurrent neural network (RNN). The RNN may calculate an error representative of the noise based partly on the input signal to be transmitted and a feedback signal to generate filter coefficient data associated with the power amplifier noise. The feedback signal is provided, after processing through the receiver, to the RNN. During an uplink TTI, the amplified input data may also be transmitted as the RF wireless transmission via an RF antenna. During a downlink TTI, the switch path may be deactivated and the receiver stage may receive an additional RF wireless transmission to be processed in the receiver stage.

公开(公告)号：US10956315B2

公开(公告)日：2021-03-23

申请号：US16043921

申请日：2018-07-24

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: G06F12/02 ,  G06F12/0893 ,  G06F12/0864 ,  G06F12/06

Abstract: Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

公开(公告)号：US20210075464A1

公开(公告)日：2021-03-11

申请号：US16561868

申请日：2019-09-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo

IPC: H04B1/525 ,  H04L5/14 ,  H04L25/03 ,  H04L27/26

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of full duplex compensation with a self-interference noise calculator. The self-interference noise calculator may be coupled to antennas of a wireless device and configured to generate adjusted signals that compensate self-interference. The self-interference noise calculator may include a network of processing elements configured to combine transmission signals into intermediate results according to input data and delayed versions of the intermediate results. Each set of intermediate results may be combined in the self-interference noise calculator to generate a corresponding adjusted signal. The adjusted signal is received by a corresponding wireless receiver to compensate for the self-interference noise generated by a wireless transmitter transmitting on the same frequency band as the wireless receiver is receiving.

公开(公告)号：US20210026644A1

公开(公告)日：2021-01-28

申请号：US17065749

申请日：2020-10-08

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Aaron P. Boehm ,  Fa-Long Luo

IPC: G06F9/38 ,  G06F9/30 ,  G11C7/10 ,  G11C7/08

Abstract: Systems, apparatuses, and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.