公开(公告)号：US20130219094A1

公开(公告)日：2013-08-22

申请号：US13399915

申请日：2012-02-17

Applicant: Gavin J. Stark ,  Steven W. Zagorianakos

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F13/20

CPC classification number: G06F13/20 ,  G06F13/385

Abstract: The functional circuitry of a network flow processor is partitioned into a number of rectangular islands. The islands are disposed in rows. A configurable mesh data bus extends through the islands. A first island includes a first memory and a first data bus interface. A second island includes a processor, a second memory, and a second data bus interface. The processor can issue a command for a target memory to do an action. If a field in the command has a first value then the target memory is the first memory, whereas if the field has a second value then the target memory is in the second memory. The command format is the same, regardless of whether the target memory is local or remote. If the target memory is remote, then a data bus bridge adds destination information before putting the command onto the global configurable mesh data bus.

Abstract translation: 网络流处理器的功能电路被划分成多个矩形岛。 这些岛屿排列成行。 可配置的网状数据总线延伸穿过岛。 第一岛包括第一存储器和第一数据总线接口。 第二岛包括处理器，第二存储器和第二数据总线接口。 处理器可以为目标内存发出一个命令来执行一个动作。 如果命令中的字段具有第一个值，则目标存储器是第一个存储器，而如果该字段具有第二个值，则目标存储器位于第二个存储器中。 命令格式相同，无论目标内存是本地还是远程目标内存。 如果目标存储器是远程的，则在将命令放入全局可配置的网格数据总线之前，数据总线桥接器将添加目标信息。

公开(公告)号：US20120093160A1

公开(公告)日：2012-04-19

申请号：US13337184

申请日：2011-12-26

Applicant: Johann Heinrich Tönsing ,  Roelof Nico DuToit ,  Gysbert Floris van Beek Van Leeuwen ,  Jan Niel Viljoen ,  David Wells ,  Leon Johannes Brits ,  Jan Christoffel DuToit

Inventor： Johann Heinrich Tönsing ,  Roelof Nico DuToit ,  Gysbert Floris van Beek Van Leeuwen ,  Jan Niel Viljoen ,  David Wells ,  Leon Johannes Brits ,  Jan Christoffel DuToit

IPC: H04L12/56

CPC classification number: H04L47/12 ,  H04L12/5602 ,  H04L29/06095 ,  H04L29/0653 ,  H04L29/06591 ,  H04L45/00 ,  H04L45/74 ,  H04L47/20 ,  H04L47/2483 ,  H04L47/41 ,  H04L49/3009 ,  H04L49/309

Abstract: A system and method for handling a digital electronic flow between a first and second entity in which a flow policy is determined that is to be applied to the flow and the flow is then directed along a path in accordance with the policy. An ID is supplied for each flow and a tag associated with each flow which indicates the policy to be applied to its associated flow. Flows are also associated with one another, with associated flows having associated policies. In particular the flow may be processed or forwarded. The path may include a graph structure and virtual applications.

Abstract translation: 一种用于处理第一和第二实体之间的数字电子流的系统和方法，其中确定要应用于流的流策略和流，然后根据策略沿着路径被引导。 为每个流提供ID，并且与每个流相关联的标签指示要应用于其关联流的策略。 流也相互关联，相关联的流具有相关联的策略。 特别地，流程可以被处理或转发。 该路径可以包括图形结构和虚拟应用。

公开(公告)号：US10680943B2

公开(公告)日：2020-06-09

申请号：US16042572

申请日：2018-07-23

Applicant: Netronome Systems, Inc.

Inventor： J. Niel Viljoen

IPC: H04J14/00 ,  H04L12/773 ,  H04L12/715 ,  H04L12/741

Abstract: An array of columns and rows of host server devices is mounted in a row of racks. Each device has a host processor and an exact-match packet switching integrated circuit. Packets are switched within the system using exact-match flow tables that are provisioned by a central controller. Each device is coupled by a first cable to a device to its left, by a second cable to a device to its right, by a third cable to a device above, and by a fourth cable to a device below. In one example, substantially all cables that are one meter or less in length are non-optical cables, whereas substantially all cables that are seven meters or more in length are optical cables. Advantageously, each device of a majority of the devices has four and only four cable ports, and connects only to non-optical cables, and the connections involve no optical transceiver.

公开(公告)号：US10659030B1

公开(公告)日：2020-05-19

申请号：US15874860

申请日：2018-01-18

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Benjamin J. Cahill

IPC: H03K17/00 ,  G06F13/40 ,  G06F9/46

Abstract: A transactional memory (TM) of an island-based network flow processor (IB-NFP) integrated circuit receives a Stats Add-and-Update (AU) command across a command mesh of a Command/Push/Pull (CPP) data bus from a processor. A memory unit of the TM stores a plurality of first values in a corresponding set of memory locations. A hardware engine of the TM receives the AU, performs a pull across other meshes of the CPP bus thereby obtaining a set of addresses, uses the pulled addresses to read the first values out of the memory unit, adds the same second value to each of the first values thereby generating a corresponding set of updated first values, and causes the set of updated first values to be written back into the plurality of memory locations. Even though multiple count values are updated, there is only one bus transaction value sent across the CPP bus command mesh.

公开(公告)号：US10474465B2

公开(公告)日：2019-11-12

申请号：US14267362

申请日：2014-05-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/30 ,  G06F9/38

Abstract: A pipelined run-to-completion processor executes a pop stack absolute instruction. The instruction includes an opcode, an absolute pointer value, a flag don't touch bit, and predicate bits. If a condition indicated by the predicate bits is not true, then the opcode operation is not performed. If the condition is true, then the stack of the processor is popped thereby generating an operand A. The absolute pointer value is used to identify a particular register of the stack, and the content of that particular register is an operand B. The arithmetic logic operation specified by the opcode is performed using operand A and operand B thereby generating a result, and the content of the particular register is replaced with the result. If the flag don't touch bit is set to a particular value, then the flag bits (carry flag and zero flag) are not affected by the instruction execution.

公开(公告)号：US10419348B2

公开(公告)日：2019-09-17

申请号：US15924193

申请日：2018-03-17

Applicant: Netronome Systems, Inc.

Inventor： Roelof Nico du Toit ,  Jacques Fourie ,  Peter Liudmilov Djalaliev

IPC: H04L12/801 ,  H04L29/06

Abstract: A TCP connection is established between a client and a server, such that packets communicated across the TCP connection pass through a proxy. Based at least in part on a result of monitoring packets flowing across the TCP connection, the proxy determines whether to split the TCP control loop into two TCP control loops so that packets can be inspected more thoroughly. If the TCP control loop is split, then a first TCP control loop manages flow between the client the proxy and a second TCP control loop manages flow between the proxy and the server. Due to the two control loops, packets can be held on the proxy long enough to be analyzed. In some circumstances, a decision is then made to stop inspecting. The two TCP control loops are merged into a single TCP control loop, and thereafter the proxy passes packets of the TCP connection through unmodified.

公开(公告)号：US10365681B1

公开(公告)日：2019-07-30

申请号：US15256588

申请日：2016-09-04

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F1/00 ,  G06F1/06

Abstract: A multiprocessor system includes several processors, a prefetching instruction code interface block, a prefetching data code interface block, a Shared Local Memory (SLMEM), and Clock Gapping Circuits (CGCs). Each processor has the same address map. Each fetches instructions from SLMEM via the instruction interface block. Each accesses data from/to SLMEM via the data interface block. The interface blocks and the SLMEM are clocked at a faster rate than the processors. The interface blocks have wide prefetch lines of the width of the SLMEM. The data interface block supports no-wait single-byte data writes from the processors, and also supports no-wait multi-byte data writes. An address translator prevents one processor from overwriting the stack of another. If a requested instruction or data is not available in the appropriate prefetching circuit, then the clock signal of the requesting processor is gapped until the instruction or data can be returned to the requesting processor.

公开(公告)号：US10362093B2

公开(公告)日：2019-07-23

申请号：US14151699

申请日：2014-01-09

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: H04L29/06 ,  H04L29/08

Abstract: Multiple processors share access, via a bus, to a pipelined NFA engine. The NFA engine can implement an NFA of the type that is not a DFA (namely, it can be in multiple states at the same time). One of the processors communicates a configuration command, a go command, and an event generate command across the bus to the NFA engine. The event generate command includes a reference value. The configuration command causes the NFA engine to be configured. The go command causes the configured NFA engine to perform a particular NFA operation. Upon completion of the NFA operation, the event generate command causes the reference value to be returned back across the bus to the processor.

公开(公告)号：US10341232B2

公开(公告)日：2019-07-02

申请号：US14263999

申请日：2014-04-28

Applicant: Nicolaas J. Viljoen ,  Sandra Scott-Hayward

Inventor： Nicolaas J. Viljoen ,  Sandra Scott-Hayward

IPC: H04L12/24 ,  H04L12/26 ,  H04L12/715 ,  H04L12/723 ,  H04L12/751 ,  H04L12/773 ,  H04L12/803

Abstract: A first switch in a MPLS network receives a plurality of packets. The plurality of packets are part of a pair of flows. The first switch performs a packet prediction learning algorithm on the first plurality of packets and generates packet prediction information. The first switch communicates the packet prediction information to a Network Operation Center (NOC). In response, the NOC communicates the packet prediction information to a second switch within the MPLS network utilizing OpenFlow messaging. In a first example, the NOC communicates a packet prediction control signal to the second switch. In a second example, a packet prediction control signal is not communicated. In the first example, based on the packet prediction control signal, the second switch determines if it will utilize the packet prediction information. In the second example, the second switch independently determines if the packet prediction information is to be used.

公开(公告)号：US10250528B2

公开(公告)日：2019-04-02

申请号：US14264003

申请日：2014-04-28

Applicant: Netronome Systems, Inc.

Inventor： Nicolaas J. Viljoen ,  Sandra Scott-Hayward

IPC: G06F15/173 ,  H04L12/931 ,  H04L12/751 ,  H04L12/715 ,  H04L12/723 ,  H04L12/773 ,  H04L12/24 ,  H04L12/26

Abstract: A first switch in a MPLS network receives a plurality of packets that are part of a pair of flows. The first switch performs a packet prediction learning algorithm on the first plurality of packets and generates packet prediction information that is communicated to a second switch within the MPLS network utilizing an Operations, Administration, and Maintenance (OAM) packet (message). In a first example, the first switch communicates a packet prediction information notification to a Network Operations Center (NOC) that in response communicates a packet prediction control signal to the second switch. In a second example, the first switch does not communicate a packet prediction information notification. In the first example, the second switch utilizes the packet prediction control signal to determine if the packet prediction information is to be utilized. In the second example, second switch independently determines if the packet prediction information is to be used.