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    PACKET ENGINE THAT USES PPI ADDRESSING
    2.
    发明申请
    PACKET ENGINE THAT USES PPI ADDRESSING 有权
    使用PPI寻址的PACKET发动机

    公开(公告)号：US20160057069A1

    公开(公告)日：2016-02-25

    申请号：US14464690

    申请日：2014-08-20

    Applicant: Netronome Systems, Inc.

    Inventor： Salma Mirza ,  Gavin J. Stark ,  Benjamin J. Cahill

    IPC: H04L12/863 ,  H04L12/861 ,  H04L12/935 ,  H04L12/801 ,  H04L12/747

    CPC classification number: H04L47/6245 ,  H04L45/742 ,  H04L47/35 ,  H04L47/621 ,  H04L49/3072 ,  H04L49/9063

    Abstract: Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed by a processing device. Rather than the PDRSDs managing and handling the storing of packet portions into the memory, a packet engine is provided. The PDRSDs use a PPI (Packet Portion Identifier) Addressing Mode (PAM) in communicating with the packet engine and in instructing the packet engine to store packet portions. The packet engine uses linear memory addressing to write the packet portions into the memory, and to read the packet portions from the memory.

    Abstract translation: 在网络设备内，来自多个PDRSD（分组数据接收和分离设备）的分组部分被加载到单个存储器中，使得分组部分稍后可以由处理设备处理。 管理和处理分组部分存储到存储器中的PDRSD不是提供分组引擎。 PDRSD在与分组引擎通信并指示分组引擎存储分组部分时使用PPI（分组部分标识符）寻址模式（PAM）。 分组引擎使用线性存储器寻址将分组部分写入存储器，并从存储器读取分组部分。

    Transactional memory that performs a statistics add-and-update operation
    3.
    发明授权
    Transactional memory that performs a statistics add-and-update operation 有权

    公开(公告)号：US10659030B1

    公开(公告)日：2020-05-19

    申请号：US15874860

    申请日：2018-01-18

    Applicant: Netronome Systems, Inc.

    Inventor： Gavin J. Stark ,  Benjamin J. Cahill

    IPC: H03K17/00 ,  G06F13/40 ,  G06F9/46

    Abstract: A transactional memory (TM) of an island-based network flow processor (IB-NFP) integrated circuit receives a Stats Add-and-Update (AU) command across a command mesh of a Command/Push/Pull (CPP) data bus from a processor. A memory unit of the TM stores a plurality of first values in a corresponding set of memory locations. A hardware engine of the TM receives the AU, performs a pull across other meshes of the CPP bus thereby obtaining a set of addresses, uses the pulled addresses to read the first values out of the memory unit, adds the same second value to each of the first values thereby generating a corresponding set of updated first values, and causes the set of updated first values to be written back into the plurality of memory locations. Even though multiple count values are updated, there is only one bus transaction value sent across the CPP bus command mesh.

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