公开(公告)号：US20050055467A1

公开(公告)日：2005-03-10

申请号：US10658666

申请日：2003-09-09

Applicant: Francis Campana ,  William Lo

Inventor： Francis Campana ,  William Lo

IPC: G06F15/16 ,  H02H3/05 ,  H03K19/003 ,  H04B1/74 ,  H04L7/04 ,  H04L7/10

CPC classification number: H04L7/10 ,  H04L2007/045

Abstract: A resynchronization device for an Ethernet network device with a transmitter and a receiver includes a detector that detects faulty code groups received by the receiver. A counter counts the faulty code groups that are detected by the false carrier detector during a predetermined period. A resynchronization trigger asserts a resynchronization signal if the counter exceeds a predetermined threshold during the predetermined period. The faulty code groups include false carriers, which include non-idle code groups other than frame delimiters. Alternately, the faulty code groups include idle code groups that match idle code groups generated by the transmitter of the local network device.

Abstract translation: 具有发射机和接收机的以太网网络设备的再同步装置包括检测器，其检测由接收机接收的故障码组。 计数器在预定时段内对由错误载波检测器检测到的故障代码组进行计数。 如果计数器在预定时段期间超过预定阈值，则重新同步触发断言重新同步信号。 错误的代码组包括虚假载波，其包括除帧分隔符之外的非空闲代码组。 或者，故障代码组包括与由本地网络设备的发射机生成的空闲代码组相匹配的空闲代码组。

公开(公告)号：US20050015660A1

公开(公告)日：2005-01-20

申请号：US10892707

申请日：2004-07-16

Applicant: Sehat Sutardja ,  Pantas Sutardja ,  William Lo

Inventor： Sehat Sutardja ,  Pantas Sutardja ,  William Lo

IPC: H01L21/822 ,  G06F11/20 ,  H01L21/00 ,  H01L21/66 ,  H01L21/82 ,  H01L27/00 ,  H01L27/04 ,  H03K19/177 ,  H02H3/05

CPC classification number: G01R31/317 ,  G01R31/31718 ,  G01R31/3172 ,  G11C29/848 ,  H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A self-reparable semiconductor includes multiple functional units that perform the same function and that include sub-functional units. The semiconductor includes one or more full or partial spare functional units that are integrated into the semiconductor. If a defect in a sub-functional unit is detected, then that sub-functional unit is switched out and replaced with a sub-functional unit in the full or partial spare functional unit. The reconfiguration is realized with switching devices that are associated with the sub-functional units. Defective functional or sub-functional units can be detected after assembly, during power up, periodically during operation, and/or manually.

Abstract translation: 自修复半导体包括执行相同功能并且包括子功能单元的多个功能单元。 半导体包括集成到半导体中的一个或多个全部或部分备用功能单元。 如果检测到子功能单元中的缺陷，那么该子功能单元被切换并且被全部或部分备用功能单元中的子功能单元替换。 通过与子功能单元相关联的开关设备来实现重新配置。 可以在组装，上电，定期运行和/或手动期间检测功能或子功能单元的不良。

公开(公告)号：US06587558B2

公开(公告)日：2003-07-01

申请号：US09772342

申请日：2001-01-29

Applicant: William Lo

Inventor： William Lo

IPC: H04M300

CPC classification number: H04M3/5183 ,  H04M3/493 ,  H04M3/5125 ,  H04M7/128

Abstract: A virtual interactive response (VIR) system mimics and enhances interactive voice response (IVR) technology by using humans to drive the voice recognition unit (VRU) speech recognition functionality. This VIR system initiates a dialogue with the customer by prompting the customer with an initial welcoming message. Calls from a customer are initially made in a first region having high labor costs, but are then directed to an overseas location using voice over Internet protocol (VOIP) or other voice communications technology. The calls are then directed to an appropriate human agent at the overseas location who then listens to the customer's query and makes a decision on how to respond to the customer.

公开(公告)号：US6023476A

公开(公告)日：2000-02-08

申请号：US791180

申请日：1997-01-31

Applicant: William Lo

Inventor： William Lo

IPC: H04L12/44 ,  H04L12/413

CPC classification number: H04L12/44

Abstract: A logical repeater set provides for delaying a character of data that passes through the logical repeater set from a receive channel in a receiving repeater set to a set of transmit channels in transmitting repeater sets. In providing for the delay of a character, the receiving repeater set calculates a receive channel character delay value, and receives a character that is to be provided on a transmit channel. The receiving repeater set then delays the character for a period of time equal to the receive channel character delay value and providing the character to the transmitting repeater set. Each transmitting repeater set further calculates a set of transmit channel character delay values for a set of transceivers. Each transmitting repeater set receives a character from the receiving repeater set that is to be provided on a transmit channel and further delays the character by a transmit channel character delay value. A receiving repeater set and transmitting repeater set may be either the same repeater set or a pair of repeater sets that are coupled together via an expansion bus.

Abstract translation: 逻辑中继器集合用于将在接收转发器中的接收信道中通过逻辑中继器集合的数据的字符延迟到发送中继器集合中的一组发送信道。 在提供字符的延迟时，接收中继器组计算接收信道字符延迟值，并且接收要在发送信道上提供的字符。 接收中继器设置然后将字符延迟等于接收信道字符延迟值的时间段，并将字符提供给发送中继器组。 每个发送中继器组进一步计算一组收发机的一组发送信道字符延迟值。 每个发送中继器组从要在发送信道上提供的接收转发器集合接收字符，并且通过发送信道字符延迟值进一步延迟该字符。 接收中继器设置和发送中继器组可以是相同的中继器组或经由扩展总线耦合在一起的一对中继器组。

公开(公告)号：US5598418A

公开(公告)日：1997-01-28

申请号：US337633

申请日：1994-11-10

Applicant: William Lo ,  Stephen McRobert

Inventor： William Lo ,  Stephen McRobert

IPC: G09G3/22 ,  G09G3/14 ,  H04L12/26 ,  H04J3/14

CPC classification number: H04L43/0817 ,  G09G3/14

Abstract: An interface to an indicator array for providing status information from a repeater used in a computer network. The interface multiplexes status value signals from the repeater provided to a group of enabled source buffers driving columns of the array. Rows of the array are driven by status enable signals from a sink buffer attached to each row. LEDs of the array have an anode connected to a source buffer and a cathode connected to a sink buffer. Cycling through the source buffer groups and status enable signals provides a 10% duty cycle for each indicator. When status values change more frequently than about once per millisecond, a pulse stretcher is used to extend the perceived duration of the status indication.

Abstract translation: 指示器阵列的接口，用于从计算机网络中使用的中继器提供状态信息。 该接口将提供的转发器的状态值信号复用到驱动数组列的启用源缓冲器组。 阵列的行由附加到每一行的接收缓冲器的状态使能信号驱动。 阵列的LED具有连接到源缓冲器的阳极和连接到宿缓冲器的阴极。 循环通过源缓冲组和状态使能信号为每个指示器提供10％的占空比。 当状态值比每毫秒更频繁地改变大约一次时，脉冲展开器用于延长状态指示的感知持续时间。

公开(公告)号：US5592486A

公开(公告)日：1997-01-07

申请号：US406081

申请日：1995-03-17

Applicant: William Lo ,  Ian S. Crayford

Inventor： William Lo ,  Ian S. Crayford

IPC: H04L12/26 ,  H04L12/44 ,  H04J3/24

CPC classification number: H04L43/00 ,  H04L12/2602 ,  H04L12/44

Abstract: A method and apparatus for efficiently transferring a data packet on a network. The efficient transfer of data includes compressing the data as the data packet is transmitted from a repeater to a management unit by determining if a destination address of a received packet matches a stored management unit address. When the stored address does not match the destination address, the data packet is compressed. The apparatus includes a repeater, a management unit, and a packet compression mechanism. The apparatus further includes comparator circuit means for determining address comparisons and count comparisons to control data compression.

Abstract translation: 一种用于在网络上有效地传送数据分组的方法和装置。 数据的有效传输包括当数据分组从中继器发送到管理单元时，通过确定接收到的分组的目的地址是否与存储的管理单元地址匹配来压缩数据。 当存储的地址与目标地址不匹配时，数据包被压缩。 该装置包括中继器，管理单元和分组压缩机制。 该装置还包括用于确定地址比较和计数比较以控制数据压缩的比较器电路装置。