Abstract:
A pulse width modulated current control method and system architecture may achieve the high performance of an advanced current control for full-bridge stages, in terms of accuracy, error, speed, and frequency response, but with a reduced complexity in terms of used analog circuits, being comparable with that of an elementary peak current control. The only analog blocks used may be a current sense transducer, i.e. a series resistor or a sense-FET, and a comparator for the current sensing while the rest of the control circuitry is digital.
Abstract:
A method of processing digital source images, each represented by pixel matrices, to obtain from two or more source images, representing one and the same real scene and acquired by utilizing different exposure levels, a final digital image capable of reproducing the real scene with an exposure latitude greater than that of each of the source images. The method, which can be advantageously used in digital still cameras, produces the final image by combining the source images with the help of a weighted average constructed pixel by pixel. Thanks to a special filtering to which the weighting coefficients are subjected before the weighted mean operation, the method obtains a final image in which the source images are harmoniously combined with each other.
Abstract:
A switched capacitor digital to analog converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of first and second reference voltage terminals. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first and second reference voltage terminals. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal. The coupling capacitor and capacitance means have capacitances, Cs and CATT respectively, that substantially satisfy the relationship: (2pnull1)nullCsnullCATTnull2pnullC, where p is the number of bits coded in the first converter segment and C is the unit capacitance.