公开(公告)号：US5257383A

公开(公告)日：1993-10-26

申请号：US743691

申请日：1991-08-12

申请人： Joseph M. Lamb

发明人： Joseph M. Lamb

IPC分类号： G06F9/48 ,  G06F13/26 ,  G06F9/46

CPC分类号： G06F13/26

摘要： A programmable, multi-level interrupt priority encoder which fields interrupts from connected devices, e.g., DMA engine, scanner, and timer, and signals an interrupt value, or priority level, associated with that device. These levels, which may range from zero to seven or more, depending upon the system with which it is applied, are used by the CPU to determine which of the plural interrupting devices to service. Using the encoder of the invention, multiple devices can be set at the same priority level.

公开(公告)号：US5220668A

公开(公告)日：1993-06-15

申请号：US723065

申请日：1991-06-28

申请人： Charles A. Bullis

发明人： Charles A. Bullis

IPC分类号： G06F11/16 ,  G06F11/273 ,  G06F11/30

CPC分类号： G06F11/16 ,  G06F11/2736 ,  G06F11/3051 ,  G06F11/3055

摘要： A state machine in a digital data processor in a UNIX-type operating system environment has state managers associated with the functional units of the data processor for indicating the state of the units; a message handler for, alternately, (a) generating requests for processing event messages indicative of conditions in the processor, that are awaiting processing and (b) generating a request for evaluation of one state manager's maintenance state, limited to transition from one state to another; and a scheduling means responsive to requests from the message handler for selectively processing the event messages, to the passage of time, and to changes of state of state managers, and for scheduling evaluation of a state manager's maintenance state. The scheduling means schedules evaluation of respective state manager's maintenance states according to a priority determined by (a) dependencies between state managers, wherein one state manager is dependent on another state manager, and (b) priorities set by scheduling conditions registered by state managers. The scheduling means executes the steps of (a) evaluating a predetermined input condition, (b) selectively making a state transition in accord with that input condition and the state manager's maintenance state, and (c) selectively performing a predetermined action associated with said transition.

摘要翻译： UNIX型操作系统环境中的数字数据处理器中的状态机具有与数据处理器的功能单元相关联的状态管理器，用于指示单元的状态; 一个消息处理程序，用于（a）产生处理表示处理器中的条件的事件消息的请求的等待处理的请求，以及（b）产生一个状态管理器的维护状态的评估请求，限于从一个状态转换到 另一个; 以及响应于来自消息处理器的请求的调度装置，用于选择性地处理事件消息，时间的流逝以及状态管理器的状态改变，以及用于调度对状态管理器的维护状态的评估。 调度装置根据由（a）状态管理器之间的依赖关系确定的优先级来对各个状态管理者的维护状态进行调度，其中一个状态管理器依赖于另一个状态管理器，以及（b）由状态管理器注册的调度条件设置的优先级。 调度装置执行以下步骤：（a）评估预定输入条件，（b）根据该输入条件和状态管理器的维护状态选择性地进行状态转换，以及（c）选择性地执行与所述转换相关联的预定动作 。

公开(公告)号：US5049701A

公开(公告)日：1991-09-17

申请号：US414107

申请日：1989-09-28

申请人： Edward R. Vowles ,  Daniel J. Calanni

发明人： Edward R. Vowles ,  Daniel J. Calanni

IPC分类号： H05K5/02 ,  H05K9/00

CPC分类号： H05K9/0062

摘要： An improved cabinet for electromagnetic and radio-frequency interference suppression includes an electrical component-mounting rail that includes a series of spring-like conductive projections or tabs internally formed to extend from its surface. The projections are arranged so that, as a component panel is mounted against the rail, the projections contact the panel at a plurality of points, establishing electrical contact between it and the rail. The projections are positioned to maintain distances between radiation-suppressing low impedance contacts of the rail and component which are small in comparison to wavelength of interference generated by the component and, thereby, to attenuate emissions from the cabinet.

公开(公告)号：US5630056A

公开(公告)日：1997-05-13

申请号：US309210

申请日：1994-09-20

申请人： Charles J. Horvath ,  William I. Leavitt ,  Mark D. Tetreault ,  Gregory M. Green ,  Peter C. Churchill

发明人： Charles J. Horvath ,  William I. Leavitt ,  Mark D. Tetreault ,  Gregory M. Green ,  Peter C. Churchill

IPC分类号： G06F13/00 ,  G06F11/16 ,  G06F11/00

CPC分类号： G06F11/1625 ,  G06F11/1633

摘要： A digital data processing device includes a bus for transmitting signals (e.g., data and/or address information) between plural functional units (e.g., a central processing unit and a peripheral controller). A first such unit includes first and second processing sections that concurrently apply to the bus complementary portions of like information signals (e.g., longwords containing data). A fault detection element reads the resultant signal from the bus and compares it with at least portions of the corresponding signals originally generated by the processing sections themselves. If there is discrepancy, the fault-detector signals a fault, e.g., causing the unit to be taken off-line. By use of a redundant unit, processing can continue for fault-tolerant operation.

摘要翻译： 数字数据处理装置包括用于在多个功能单元（例如，中央处理单元和外围控制器）之间传送信号（例如，数据和/或地址信息）的总线。 第一这样的单元包括同时应用于类似信息信号的总线互补部分（例如，包含数据的长字）的第一和第二处理部分。 故障检测元件从总线读取合成信号并将其与最初由处理部分本身产生的对应信号的至少部分进行比较。 如果存在差异，则故障检测器发出故障信号，例如使单元离线。 通过使用冗余单元，处理可以继续进行容错操作。

公开(公告)号：US5020024A

公开(公告)日：1991-05-28

申请号：US003732

申请日：1987-01-16

申请人： Jeffrey L. Williams

发明人： Jeffrey L. Williams

IPC分类号： G06F11/18 ,  G06F11/16 ,  G06F15/16 ,  G06F15/177

CPC分类号： G06F11/1679

摘要： Digital logic equipment in which two logic elements operate with timing control from a clock element with selected synchronism, includes a failure detecting element which detects the absence of the selected synchronism between the two logic elements even when each is providing otherwise correct logic operation. The apparatus and method enable a digital logic system to follow two redundant digital logic elements so long as they operate in lock step synchronism, and to sense a failure which occurs only in synchronism to disable one of the two logic elements to maintain thereafter uninterrupted operation with the other logic element.

摘要翻译： 其中两个逻辑元件与来自具有所选同步的时钟元件的定时控制一起操作的数字逻辑设备包括故障检测元件，即使当每个逻辑元件提供另外正确的逻辑运算时也检测到两个逻辑元件之间所选同步的不存在。 该装置和方法使得数字逻辑系统能够遵循两个冗余数字逻辑元件，只要它们以锁定步骤同步操作，并且感测仅在同步地发生的故障以禁用两个逻辑元件中的一个来维持其后不间断的操作， 另一个逻辑元素。

公开(公告)号：US4931922A

公开(公告)日：1990-06-05

申请号：US79218

申请日：1987-07-29

申请人： Kurt F. Baty ,  Joseph M. Lamb

发明人： Kurt F. Baty ,  Joseph M. Lamb

IPC分类号： G06F13/00 ,  G06F1/04 ,  G06F3/00 ,  G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/22 ,  G06F13/36 ,  G06F13/42

CPC分类号： G06F11/2017 ,  G06F11/0745 ,  G06F11/0793 ,  G06F11/1402 ,  G06F11/1604 ,  G06F11/1625 ,  G06F11/2005 ,  G06F11/2007 ,  G06F11/22 ,  G06F13/423 ,  G06F1/04 ,  G06F11/10 ,  G06F11/1629 ,  G06F11/1666 ,  G06F11/20

摘要： A fault-tolerant digital data processing system comprises at least a first peripheral controller communicating with at least one peripheral device over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing signals. The first peripheral controller includes a first device interface element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The first device interface element also receives, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses. A second peripheral controller is coupled to the peripheral device bus for receiving the first and second input signals identically with the first peripheral controller. The second peripheral controller includes a second device interface element for applying at least one of those input signals to the second input/output controller. Circuitry is coupled to the first and second bus interface elements for responding to operational states of those elements to generate a signal indicative of their synchronous receipt of identical copies the first and second input signals.

摘要翻译： 容错数字数据处理系统至少包括通过具有第一和第二输入/输出总线的外围设备总线与至少一个外围设备进行通信的第一外围控制器，每个总线承载数据，地址，控制和定时信号。 第一外围控制器包括第一设备接口元件，用于同步地并且同时地向第一和第二输入/输出总线施加重复的信息信号以传输到外围设备。 第一设备接口元件在没有故障的情况下还从第一和第二输入/输出总线同步并同时接收重复信息信号。 第二外围控制器耦合到外围设备总线，用于与第一外围控制器相同地接收第一和第二输入信号。 第二外围控制器包括用于将这些输入信号中的至少一个施加到第二输入/输出控制器的第二设备接口元件。 电路耦合到第一和第二总线接口元件，用于响应这些元件的操作状态，以产生指示其同步接收相同副本的第一和第二输入信号的信号。

公开(公告)号：US4453215A

公开(公告)日：1984-06-05

申请号：US307525

申请日：1981-10-01

申请人： Robert Reid

发明人： Robert Reid

IPC分类号： G06F11/18 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F13/00 ,  G06F13/374

CPC分类号： G06F11/1625 ,  G06F11/1641 ,  G06F11/2007 ,  G06F13/374 ,  G06F11/10 ,  G06F11/20

摘要： A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

摘要翻译： 容错计算机系统在计算模块的单元之间提供在所有单元共同的总线结构上的信息传输，包括处理器单元和存储器单元以及一个或多个外围控制单元。 在总线结构和每个单元中，系统的信息处理部分可以具有重复的伙伴。 错误检测器检查总线结构和每个系统单元的操作，仅在无故障总线导体和无故障单元之间提供信息传输。 计算机系统可以通过仅使用无故障的导体和功能单元在基本上不发生故障的情况下以这种方式操作。 具有异常速度和简单性的仲裁电路提供计算模块的单元根据每个单元的优先级访问公共总线结构。 模块的单元检查输入和输出信号是否有错误，向其他模块单元发出检测到的错误信号，并禁止单元向总线结构发送潜在的错误信息。

公开(公告)号：US6128196A

公开(公告)日：2000-10-03

申请号：US69025

申请日：1998-04-27

申请人： Willard O. Hoyle, Jr. ,  Robert Craig Abraham ,  Keith A. St. Pierre ,  Vincent T. Curran

发明人： Willard O. Hoyle, Jr. ,  Robert Craig Abraham ,  Keith A. St. Pierre ,  Vincent T. Curran

IPC分类号： H05K7/14 ,  H05R5/00

CPC分类号： H05K7/1409 ,  H05K7/1439

摘要： A chassis system for housing a plurality of circuit boards, such as PCI standard bus boards, provides a rack-mountable chassis having an open front side and a motherboard with a plurality of board connectors arranged side-by-side with respect to the front end. The boards are mounted in individual frameworks that facilitate ready installation and removal from the chassis. In particular, the chassis includes a plurality of receiving blocks at the bottom rear of the chassis, aligned with each of the motherboard connectors. The receiving blocks receive pivots mounted on the back of each framework. The framework is inserted into, and removed from the front opening of the chassis in an upwardly pivoted position that clears the motherboard connectors and other obstructions in the chassis. The framework is pivoted into and out of engagement with the motherboard when the pivot is located in the receiving blocks. The chassis can include top-mounted tracks. The tracks receive rollers on the framework. When the framework is fully inserted into the chassis, the rear rollers lower the rear of the framework, having moved down a ramp. The front rollers can be selectively lowered and raised by actuating a movable bracket.

摘要翻译： 用于容纳诸如PCI标准总线板的多个电路板的底架系统提供了具有敞开的前侧的可机架安装的底盘和具有相对于前端并排布置的多个板连接器的母板 。 这些板安装在各个框架中，便于从机箱进行安装和拆卸。 特别地，底盘包括在底盘的后部的多个接收块，与每个主板连接器对准。 接收块接收安装在每个框架背面的枢轴。 框架在向上枢转的位置插入到底架的前开口中并从底座的前开口移除，从而清除主板连接器和底盘中的其它障碍物。 当枢轴位于接收块中时，框架枢转进入和离开与主板的接合。 底盘可以包括顶部安装的轨道。 轨道在框架上接收滚筒。 当框架完全插入底盘时，后滚轮将框架的后部降下，沿斜坡移动。 可以通过致动可动支架来选择性地降低和升高前辊。

公开(公告)号：US5968185A

公开(公告)日：1999-10-19

申请号：US116770

申请日：1998-07-16

申请人： Thomas C. Bressoud ,  John E. Ahern ,  Kenneth P. Birman ,  Robert C. B. Cooper ,  Bradford B. Glade ,  Fred B. Schneider ,  John D. Service

发明人： Thomas C. Bressoud ,  John E. Ahern ,  Kenneth P. Birman ,  Robert C. B. Cooper ,  Bradford B. Glade ,  Fred B. Schneider ,  John D. Service

IPC分类号： G06F11/16 ,  G06F11/20 ,  G06F11/00

CPC分类号： G06F11/2097 ,  G06F11/1482 ,  G06F11/2023

摘要： In a fault-tolerant computer system, a primary replica supervisor is interposed between an operating system and a primary replica of an application program being executed by a primary processor. An object-code editor locates calls to the operating system and loops in the application program and inserts instruction sequences that enable the replica supervisor to intercept the calls to the operating system, results returned by the operating system as a result of the calls and asynchronous events delivered by the operating system to the replica. A backup replica supervisor is similarly interposed between an operating system and a backup replica of the application program being executed by a backup processor. The primary replica interacts with an environment. The replica supervisors ensure that the backup replica undergoes state transformations, as a result of the calls to the operating system and asynchronous events, that are equivalent to state transformations that the primary replica undergoes as a result of corresponding calls and asynchronous events. Thus, after a failure in the primary processor, the backup replica can interact with the environment in a manner consistent with interactions between the primary replica and the environment prior to the failure.

摘要翻译： 在容错计算机系统中，主复制主管介于操作系统和由主处理器执行的应用程序的主副本之间。 对象代码编辑器定位到操作系统的调用并在应用程序中循环，并插入指令序列，使得副本管理器能够拦截对操作系统的调用，由于调用和异步事件，操作系统返回的结果 由操作系统交付给副本。 备份副本管理程序类似地插入在由备份处理器执行的应用程序的操作系统和备份副本之间。 主要副本与环境交互。 由于对操作系统和异步事件的调用，副本监视器确保备份副本经历状态转换，这些转换等效于主副本作为相应调用和异步事件的结果进行的状态转换。 因此，在主处理器发生故障之后，备份副本可以以与故障之前主要副本和环境之间的交互一致的方式与环境进行交互。

公开(公告)号：US5802265A

公开(公告)日：1998-09-01

申请号：US565145

申请日：1995-12-01

申请人： Thomas C. Bressoud ,  John E. Ahern ,  Kenneth P. Birman ,  Robert C. B. Cooper ,  Bradford B. Glade ,  Fred B. Schneider ,  John D. Service

发明人： Thomas C. Bressoud ,  John E. Ahern ,  Kenneth P. Birman ,  Robert C. B. Cooper ,  Bradford B. Glade ,  Fred B. Schneider ,  John D. Service

IPC分类号： G06F11/16 ,  G06F11/20 ,  G06F11/34

CPC分类号： G06F11/2097 ,  G06F11/1482 ,  G06F11/2023

摘要： In a fault-tolerant computer system, a primary replica supervisor is interposed between an operating system and a primary replica of an application program being executed by a primary processor. An object-code editor locates calls to the operating system and loops in the application program and inserts instruction sequences that enable the replica supervisor to intercept the calls to the operating system, results returned by the operating system as a result of the calls and asynchronous events delivered by the operating system to the replica. A backup replica supervisor is similarly interposed between an operating system and a backup replica of the application program being executed by a backup processor. The primary replica interacts with an environment. The replica supervisors ensure that the backup replica undergoes state transformations, as a result of the calls to the operating system and asynchronous events, that are equivalent to state transformations that the primary replica undergoes as a result of corresponding calls and asynchronous events. Thus, after a failure in the primary processor, the backup replica can interact with the environment in a manner consistent with interactions between the primary replica and the environment prior to the failure.