FREQUENCY CALIBRATION CIRCUIT FOR AUTOMATICALLY CALIBRATING FREQUENCY AND METHOD THEREOF
    11.
    发明申请
    FREQUENCY CALIBRATION CIRCUIT FOR AUTOMATICALLY CALIBRATING FREQUENCY AND METHOD THEREOF 有权
    用于自动校准频率的频率校准电路及其方法

    公开(公告)号:US20120056651A1

    公开(公告)日:2012-03-08

    申请号:US12907013

    申请日:2010-10-18

    IPC分类号: H03L7/08

    CPC分类号: H03L7/08

    摘要: A serial interface engine generates a series of digital data according to a pair of differential signals received from a high-speed Universal Serial Bus host and/or a full-speed universal serial bus host. Then, a packet identification (PID) unit identifies a packet identification of a start of each frame and a first period between two consecutive packet identifications according to the series of digital data. A count comparator is used for generating a calibration signal to calibrate an output frequency of an oscillator according to the first period.

    摘要翻译: 串行接口引擎根据从高速通用串行总线主机和/或全速通用串行总线主机接收的一对差分信号产生一系列数字数据。 然后,分组识别(PID)单元根据该系列数字数据来识别每帧开始的包标识和两个连续分组标识之间的第一周期。 计数比较器用于产生校准信号以校准根据第一周期的振荡器的输出频率。

    Frequency calibration circuit for automatically calibrating a frequency generated by an oscillator and method thereof
    12.
    发明授权
    Frequency calibration circuit for automatically calibrating a frequency generated by an oscillator and method thereof 有权
    用于自动校准由振荡器产生的频率的频率校准电路及其方法

    公开(公告)号:US08359489B2

    公开(公告)日:2013-01-22

    申请号:US12907013

    申请日:2010-10-18

    IPC分类号: G06F1/12

    CPC分类号: H03L7/08

    摘要: A serial interface engine generates a series of digital data according to a pair of differential signals received from a high-speed Universal Serial Bus host and/or a full-speed universal serial bus host. Then, a packet identification (PID) unit identifies a packet identification of a start of each frame and a first period between two consecutive packet identifications according to the series of digital data. A count comparator is used for generating a calibration signal to calibrate an output frequency of an oscillator according to the first period.

    摘要翻译: 串行接口引擎根据从高速通用串行总线主机和/或全速通用串行总线主机接收的一对差分信号产生一系列数字数据。 然后,分组识别(PID)单元根据该系列数字数据来识别每帧开始的包标识和两个连续分组标识之间的第一周期。 计数比较器用于产生校准信号以校准根据第一周期的振荡器的输出频率。

    USB 3.0 HOST WITH LOW POWER CONSUMPTION AND METHOD FOR REDUCING POWER CONSUMPTION OF A USB 3.0 HOST
    13.
    发明申请
    USB 3.0 HOST WITH LOW POWER CONSUMPTION AND METHOD FOR REDUCING POWER CONSUMPTION OF A USB 3.0 HOST 有权
    具有低功耗的USB 3.0主机和用于降低USB 3.0主机功耗的方法

    公开(公告)号:US20120324261A1

    公开(公告)日:2012-12-20

    申请号:US13481861

    申请日:2012-05-27

    IPC分类号: G06F1/32

    摘要: A USB 3.0 host with low power consumption includes a super speed circuit, a non-super speed circuit, and a control module. The super speed circuit is used for transmitting data at a first transmission speed. A default state of the super speed circuit is turning-off. The non-super speed circuit is used for transmitting data at a second transmission speed, a third transmission speed, or a fourth transmission speed. The first transmission speed is faster than the second transmission speed, the third transmission speed, and the fourth transmission speed. The control module is used for detecting whether a USB peripheral device is connected to the USB 3.0 host, and controlling turning-on and turning-off of the super speed circuit.

    摘要翻译: 具有低功耗的USB 3.0主机包括超速电路,非超速电路和控制模块。 超速电路用于以第一传输速度发送数据。 超速电路的默认状态是关闭。 非超速电路用于以第二传输速度,第三传输速度或第四传输速度传输数据。 第一传输速度比第二传输速度,第三传输速度和第四传输速度快。 控制模块用于检测USB外围设备是否连接到USB 3.0主机,并控制超速电路的导通和关断。