Abstract:
In an optimal recording power calibration method for improving seeking stability on a recording power calibration area, a specific area serves as a data recording area during an optimal recording power calibration, wherein a length of the specific area is such that a plurality of times of optimal recording power calibrations can be performed. The method includes: an optimal recording power calibration step of recording, with different recording power, a first length of calibration data in the specific area, and calibrating optimal recording power, wherein a data sector recorded in this step is defined as a calibration recording sector; and a data recording step of recording, with data recording power, a second length of information having a logical address beside the calibration recording sector of the specific area, wherein a data sector recorded in the step is defined as an information recording sector.
Abstract:
A display device and a configuration of common electrode thereof are provided. The display device and the configuration of common electrode thereof are used for dividing the common electrode connected to an electrostatic discharge protection circuit into two conducting wires and electrically connecting two conducting wires between two corresponding adjacent signal lines to form a net structure. Thus, the aforementioned configuration is able to repair the short circuits occurring between several common electrodes and several signal lines, thereby increasing the yield rate of the display device.
Abstract:
An active matrix substrate including a substrate, a pixel array, and a peripheral circuit is provided. The substrate has a display region and a peripheral circuit region adjacent thereto. The pixel array is disposed in the display region. The peripheral circuit is disposed in the peripheral circuit region and includes a first signal line, a second signal line, a first bypass-line, a second bypass-line, a plurality of chip bonding pads, a first dummy bonding pad and a plurality of second dummy bonding pads. The first bypass-line and the first signal line transmit the same signal. The second bypass-line and the second signal line transmit the same signal. The chip bonding pads are disposed between the bypass-lines and the pixel array, and are connected to the pixel array. The first dummy bonding pad is connected to the first bypass-line. Each second dummy bonding pad is connected to the second bypass-line.
Abstract:
A method for detecting a defect of an optical disc includes steps of: confirming an optical pickup head being accessing data in a track on state; determining a defective region of the optical disc according to a peak-to peak value of a wobble signal; and, maintaining the optical pickup head being unchanged when the defective region is detected.
Abstract:
A liquid crystal display device that comprises a plurality of gate lines formed in parallel to each other, a plurality of source lines formed in parallel to each other and orthogonal to the gate lines, an array of cells formed in rows and columns, each of the cells being formed near an intersection of one of the gate lines and one of the source lines, a first transistor of each of the cells disposed at an N-th row and M-th column, N and M being integers, driven by an (N-2)-th gate line, and a second transistor of the each of the cells driven by an N-th gate line.
Abstract:
A board adjuster is provided, including an adjusting member and a positioning member. The adjusting member includes a toggling portion and an insertion portion, the insertion portion has two restricting members extending oppositely, the toggling portion has two recessive portions, and the insertion portion is located between two recessive portions. The positioning member has a slot. The insertion portion is for being inserted into a gap between two boards, the positioning member is for abutting against and between the two boards and the toggling portion, the insertion portion is disposed through the slot, the positioning member is disposed through the two recessive portions, the positioning member abuts against the two recessive portions so that the two restricting members respectively abut against a side of one of the two boards away from the toggling portion.
Abstract:
In an optimal recording power calibration method for improving seeking stability on a recording power calibration area, a specific area serves as a data recording area during an optimal recording power calibration, wherein a length of the specific area is such that a plurality of times of optimal recording power calibrations can be performed. The method includes: an optimal recording power calibration step of recording, with different recording power, a first length of calibration data in the specific area, and calibrating optimal recording power, wherein a data sector recorded in this step is defined as a calibration recording sector; and a data recording step of recording, with data recording power, a second length of information having a logical address beside the calibration recording sector of the specific area, wherein a data sector recorded in the step is defined as an information recording sector.
Abstract:
In an optimal recording power calibration method for improving seeking stability on a recording power calibration area, a specific area serves as a data recording area during an optimal recording power calibration, wherein a length of the specific area is such that a plurality of times of optimal recording power calibrations can be performed. The method includes: an optimal recording power calibration step of recording, with different recording power, a first length of calibration data in the specific area, and calibrating optimal recording power, wherein a data sector recorded in this step is defined as a calibration recording sector; and a data recording step of recording, with data recording power, a second length of information having a logical address beside the calibration recording sector of the specific area, wherein a data sector recorded in the step is defined as an information recording sector.
Abstract:
A liquid crystal display array. The liquid crystal display array has a plurality of gate lines, a plurality of source lines and a plurality of cells. Each gate line comprises a first portion and a second portion extended from the first portion. Each cell corresponds to the interlaced data line and scan line and has a first storage capacitor. A first electrode of the first storage capacitor corresponding to a first gate line of the gate lines is coupled to the first portion or the second portion of any gate line except the first gate line.
Abstract:
The invention is to provide an auxiliary circuit for power factor corrector (PFC) having self-power supplying and zero current detection (ZCD) mechanisms, which comprises a filter capacitor electrically coupled to a secondary winding of an inductor of the auxiliary circuit installed in a power supply and two resistors respectively coupled the positive and negative terminals of the filter capacitor in series with a ZCD pin of a PFC. Such that the secondary winding can be shared by the ZCD and the power supply pins of the PFC to eliminate a necessity of providing an additional ZCD winding and reduce the complexity of circuitry, the manufacturing cost, and a size of power supply without sacrificing power.