MULTIPLE HOST MEMORY CONTROLLER
    14.
    发明公开

    公开(公告)号:US20230161506A1

    公开(公告)日:2023-05-25

    申请号:US17987092

    申请日:2022-11-15

    CPC classification number: G06F3/0659 G06F3/0604 G06F3/0656 G06F3/0673

    Abstract: Multiple (e.g., two) hosts access a single memory channel (and/or device) via a memory controller. The single memory channel/device can support at most one access at a time. To reduce contention between the multiple hosts, the memory controller comprises multiple (e.g., two), independent, host ports. Each host port is associated with a write buffer(s) in the memory controller that stores write data at least until the memory controller writes the data to the memory channel. Data stored in a write buffer may be used to respond to memory access commands (e.g., reads or writes) on the ports without accessing the memory channel. In this manner, the hosts do not directly contend with each other for the single memory channel or the memory controller.

    Generating an authentication result by using a secure base key

    公开(公告)号:US11539535B2

    公开(公告)日:2022-12-27

    申请号:US16339172

    申请日:2017-10-05

    Abstract: An encrypted sequence that includes an authentication key may be received. A base key stored at a device may be identified and the encrypted sequence may be decrypted with the base key to obtain the authentication key. A challenge value may be received and the authentication key may be combined with the challenge value to generate a device ephemeral key. An authentication result may be generated for the device based on a combination of the device ephemeral key and the challenge value. Furthermore, the authentication result may be transmitted to a mobile network to authenticate the device.

    Using cryptographic blinding for efficient use of Montgomery multiplication

    公开(公告)号:US11522669B2

    公开(公告)日:2022-12-06

    申请号:US17042006

    申请日:2019-03-26

    Inventor: Michael Tunstall

    Abstract: Aspects of the present disclosure involves receiving an input message, generating a first random value that is used to blind the input message input message to prevent a side-channel analysis (SCA) attack, computing a second random value using the first random value and a factor used to compute the Montgomery form of a blinded input message without performing an explicit Montgomery conversion of the input message, and computing a signature using Montgomery multiplication, of the first random value and the second random value, wherein the signature is resistant to the SCA attack.

    SECURE COMPUTATION ENVIRONMENT
    18.
    发明申请

    公开(公告)号:US20220382874A1

    公开(公告)日:2022-12-01

    申请号:US17650544

    申请日:2022-02-10

    Inventor: Ambuj KUMAR

    Abstract: A container corresponding to executable code may be received. In response to receiving the container, a container manager resident in a memory of a computation environment may be executed to verify the container. The container manager may be verified by a boot loader of the computation environment. Permissions of the container to access the resources of a computation environment may be determined after the verification of the container by the container manager. Access to one or more resources of the computation environment may be provided by transferring control to the one or more resources from the container manager to the container based on the permissions of the container for the resources of the computation environment.

    Masked gate logic for resistance to power analysis

    公开(公告)号:US11386236B2

    公开(公告)日:2022-07-12

    申请号:US16427636

    申请日:2019-05-31

    Abstract: A method of and system for gate-level masking of secret data during a cryptographic process is described. A mask share is determined, wherein a first portion of the mask share includes a first number of zero-values and a second number of one-values, and a second portion of the mask share includes the first number of one-values and the second number of zero-values. Masked data values and the first portion of the mask share are input into a first portion of masked gate logic, and the masked data values and the second portion of the mask share are input into a second portion of the masked gate logic. A first output from the first portion of the masked gate logic and a second output from the second portion of the masked gate logic are identified, wherein either the first output or the second output is a zero-value.

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