公开(公告)号：US07535788B2

公开(公告)日：2009-05-19

申请号：US11636173

申请日：2006-12-08

Applicant: Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

IPC: G11C5/14

CPC classification number: G11C11/413

Abstract: A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.

Abstract translation: 公开了一种写入动态功率控制电路，其包括BL及其互补BLB，耦合到BL和BLB的至少一个存储单元，具有耦合到BL的源极，漏极和栅极的第一NMOS晶体管， Vss和第一数据信号，分别具有耦合到BLB的源极，漏极和栅极的第二NMOS晶体管，Vss和第二数据信号，其中第二数据信号与第一数据信号互补， 第一PMOS晶体管，具有源极，漏极和栅极，分别耦合到高电压电源（CVDD）节点，BLB和BL，以及第二PMOS晶体管，其具有源极，漏极和栅极耦合到 CVDD节点，BL和BLB。

公开(公告)号：US20080144419A1

公开(公告)日：2008-06-19

申请号：US11638187

申请日：2006-12-13

Applicant: Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

IPC: G11C5/14

CPC classification number: G11C11/412 ,  G11C11/413

Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.

Abstract translation: 用于集成电路模块的功率控制电路包括耦合在电源电压和集成电路模块的功率节点之间的至少一个开关装置; 以及开关控制模块，其具有耦合到所述开关装置的第一端子，耦合到控制信号的第二端子，耦合到至少一个跟踪单元的第一存储节点的第三端子，耦合到所述至少一个跟踪单元的第二存储节点的第四端子 跟踪单元和耦合到集成电路模块的功率节点的第五端子，用于根据集成电路模块的操作模式控制开关装置将电源电压传递到功率节点，具有或不具有实质的电压降 。