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11.发明授权Vital processing system including a vital power controller with forgiveness feature 失效重要的处理系统包括具有宽恕功能的重要功率控制器
公开(公告)号：US4949273A
公开(公告)日：1990-08-14
申请号：US267070
申请日：1988-11-04
CPC分类号： G06F11/0796 , G06F11/00 , G06F11/0757 , G06F11/0763
摘要： The present device, a vital power controller with forgiveness, is a subsystem of a larger vital processing system, the function of the subsystem being to verify the proper operation of the larger system and to provide power to the system outputs only when the larger system functions correctly; the larger system periodically delivers checkword sets to the vital power controller (VPC); the checkwords verify the correct operation of the larger system, a valid checkword set enabling the VPC to generate vital power for a limited time; the forgiveness feature allows the VPC to tolerate an occasional bad checkword set and yet continue to provide vital power if the rate at which bad checkword sets is encountered is below a specified rate, thereby providing improved performance in the presence of noise which tends to produce occasional bad checkwords and which would otherwise cause loss of vital power.
摘要翻译： 本设备是具有宽恕性的重要功率控制器，是较大的重要处理系统的子系统，子系统的功能是验证较大系统的正常运行，并且仅在较大系统功能时才向系统输出供电 正确的 较大的系统周期性地向重要功率控制器（VPC）提供校验字集合; 核对单词验证较大系统的正确操作，一个有效的检查词，使VPC能够在有限的时间内产生生命力; 宽恕功能允许VPC容忍偶尔的错误勾号，并且如果遇到错误的单词集的速率低于规定的速率，并且继续提供重要的功率，从而在存在噪声的情况下提供改进的性能，这倾向于偶尔产生 不好的支票，否则会导致生命力的损失。
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公开(公告)号：US4168526A
公开(公告)日：1979-09-18
申请号：US882688
申请日：1978-03-02
摘要： A microprocessor based vital delay circuit is provided which is arranged to emit an output no less than a predetermined time after an input stimulus. The predetermined time, which corresponds to the delay, is controlled by selecting the relationship between two quantities. A digital processor performs a series of computations on the two quantities, each computation is arranged to take unit time and by selecting the proper relationship between the two quantities, the total series of computations takes a predetermined amount of time. Before the output is allowed to occur, several checks are performed to insure that no hardware or software failures have erroneously generated the result. One novel checking technique insures that the clock frequency has not changed, and this technique is applicable to a wide variety of devices in which digital techniques are employed.
摘要翻译： 提供了一种基于微处理器的重要延迟电路，其被布置成在输入刺激之后发出不少于预定时间的输出。 通过选择两个量之间的关系来控制对应于延迟的预定时间。 数字处理器对两个量进行一系列计算，每个计算被设置为花费单位时间，并且通过选择两个量之间的适当关系，总计一系列计算需要预定的时间量。 在允许输出发生之前，会执行几次检查，以确保没有硬件或软件故障错误地生成结果。 一种新颖的检查技术确保时钟频率没有改变，并且该技术适用于采用数字技术的各种设备。
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