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公开(公告)号：US4157580A
公开(公告)日：1979-06-05
申请号：US874007
申请日：1978-01-31
CPC分类号： H03K5/15 , H01H47/002 , H03K5/151 , H03K5/1515 , H01H47/043 , H01H47/18
摘要： A fail-safe time delay circuit is provided to produce an output a predetermined time, and no less than a predetermined time after an input stimulus. The circuit includes a driving circuit for a pair of relays which are operated at slightly greater than 50% duty cycle and out of phase such that, except when the circuit is de-energized, at least one of the relays is always energized. The contacts of the two relays are employed in a balanced voltage amplifier to produce a bi-polar signal, with the magnitude of both polarities increasing, with the time required for the increase to a defined threshold establishing the time delay. A pair of threshold circuits are coupled to the output of the balanced voltage amplifier such that each threshold circuit (one responding to the positive portion, and the other the negative portion of the bi-polar output) is energized when the respective portion of the bi-polar signal is detected to reach the associated threshold. Each of the threshold circuits provides an input to a vital AND gate such that only when the excursion in the bi-polar signal exceeds the threshold of both threshold circuits will the vital AND gate produce an output to energize a load.
摘要翻译： 提供故障安全时间延迟电路以在输入刺激之后不小于预定时间产生预定时间的输出。 电路包括用于一对继电器的驱动电路，其以略大于50％的占空比和异相操作，使得除了当电路断电时，至少一个继电器总是通电。 两个继电器的触点用于平衡电压放大器中以产生双极性信号，两极性的大小随着增加到确定时间延迟的确定阈值所需的时间而增加。 一对阈值电路耦合到平衡电压放大器的输出端，使得每个阈值电路（一个响应于正极部分，另一个是双极输出的负极部分）被激励，当Bi 检测到极性信号以达到相关阈值。 每个阈值电路向重要的与门提供输入，使得只有当双极信号中的偏移超过两个阈值电路的阈值时，重要的“与”门才会产生一个输出以激励负载。
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2.发明授权Apparatus for vitally sensing binary data for a vital processor implemented with non-vital hardware 失效用于使用非重要硬件实现的重要处理器的二值数据的二值数据的装置
公开(公告)号：US5125090A
公开(公告)日：1992-06-23
申请号：US606894
申请日：1990-10-31
CPC分类号： B61L27/0061 , G06F11/076 , G06F11/0763 , G06F11/08 , G06F11/10 , G06F7/724
摘要： The invention describes a method and apparatus for effecting vital functions notwithstanding the fact that non-vital hardware is employed. A vital processor is implemented using non-vital hardware in the form of a digital computer which may for example be a microprocessor. The vital processor accepts binary input values and, based on a series of logical expressions relating output values to input values, determines the appropriate output values. Rather than employing a single bit to represent the condition of a particular input or output, unique multibit binary values or names are used. Each input or output has assigned to it at least two unique multibit values, each satisfying the code rules of a different code. Thus rather than representing a closed contact as a single 1 bit, and an open contact as a single 0 bit, in accordance with the invention the closed contact is represented by a unique multibit name which satisfies the code rules of a first code. At any point in the processing the value representing the contact can be checked to see if it satisfies the code rules, and if it does not a potential error is detected and handled. Before actually controlling output devices in accordance with the processing, further tests are implemented which ensure that the multibit value computed for a particular output not only satifies the predetermined code rule which is required, but is also correct bit for bit. Logic equations describing the relationship between output and input are actually computed using the multibit values as opposed to single bit values.
摘要翻译： 本发明描述了一种用于实现重要功能的方法和装置，尽管采用非重要硬件的事实。 使用数字计算机形式的非重要硬件实现重要的处理器，数字计算机可以是例如微处理器。 重要的处理器接受二进制输入值，并且基于将输出值与输入值相关联的一系列逻辑表达式，确定适当的输出值。 不使用单个位来表示特定输入或输出的条件，而是使用唯一的多位二进制值或名称。 每个输入或输出分配给至少两个唯一的多位值，每个值都满足不同代码的代码规则。 因此，根据本发明，根据本发明，不是将单个1位的闭合接点和作为单个0位的开放接点表示为满足第一代码的代码规则的唯一多位名称。 在处理的任何时刻，可以检查表示联系人的值，以查看它是否满足代码规则，并且如果不检测和处理潜在的错误。 在根据处理实际控制输出设备之前，实施进一步的测试，确保为特定输出计算的多位值不仅满足所需的预定代码规则，而且还是位的正确位。 描述输出和输入之间的关系的逻辑方程实际上是使用多位值而不是单个位值来计算的。
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公开(公告)号：US4831521A
公开(公告)日：1989-05-16
申请号：US550693
申请日：1983-11-10
申请人： David B. Rutherford
发明人： David B. Rutherford
CPC分类号： G06F11/10 , G06F11/076 , G06F11/0763 , G06F11/08 , G06F7/724
摘要： A method and apparatus for effecting vital functions notwithstanding the fact that non-vital hardware is employed. A vital processor is implemented using non-vital hardware in the form of a digital computer which may for example be a microprocessor. The vital processor accepts binary input values and, based on a series of logical expressions relating output values to input values, determines the appropriate output values. Rather than employing a single bit to represent the condition of a particular input or output, unique multibit binary values or names are used. Each input or output has assigned to it at least two unique multibit values, each satisfying the code rules of a different code. Thus rather than representing a closed contact as a single 1 bit, and an open contact as a single 0 bit, the closed contact is represented by a unique multibit name which satisfies the code rules of a first code. At any point in the processing the value representing the contact can be checked to see if it satisfies the code rules, and if it does not a potential error is detected and handled. Although it is highly unlikely that a hardware failure would result in generating one of the few multibit names satisfying the code rule, that occurrence is not unlikely enough to be considered vital. Before actually controlling output devices in accordance with the processing, further tests are implemented which ensure that the multibit value computed for a particular output not only satisfies the predetermined code rule which is required, but is also correct bit for bit. Logic equations describing the relationship between output and input are actually computed using the multibit values as opposed to single bit values.
摘要翻译： 尽管采用非重要硬件的事实，仍然用于实现重要功能的方法和装置。 使用数字计算机形式的非重要硬件实现重要的处理器，数字计算机可以是例如微处理器。 重要的处理器接受二进制输入值，并且基于将输出值与输入值相关联的一系列逻辑表达式，确定适当的输出值。 不使用单个位来表示特定输入或输出的条件，而是使用唯一的多位二进制值或名称。 每个输入或输出分配给至少两个唯一的多位值，每个值都满足不同代码的代码规则。 因此，不是将单个1位的闭合触点和作为单个0位的开放触点表示，所以闭合触点由满足第一代码的代码规则的唯一多位名称表示。 在处理的任何时刻，可以检查表示联系人的值，以查看它是否满足代码规则，并且如果不检测和处理潜在的错误。 尽管硬件故障极不可能导致产生满足代码规则的少数几个名称之一，但这种发生并不太可能被认为是至关重要的。 在根据处理实际控制输出设备之前，实施进一步的测试，确保为特定输出计算的多位值不仅满足所需的预定代码规则，而且还是位的正确位。 描述输出和输入之间的关系的逻辑方程实际上是使用多位值而不是单个位值来计算的。
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公开(公告)号：US4495578A
公开(公告)日：1985-01-22
申请号：US313926
申请日：1981-10-22
CPC分类号： B61L3/008
摘要： A vehicle carried profile generator generates a speed profile to control a vehicle governor at the transition from a higher to lower speed limit. The speed profile is calculated and checked to ensure it starts at a valid speed limit, continually decreases and is above a wayside speed limit. The governor is modified or controlled to inhibit brake application or a requirement for a brake application so long as actual speed is below profile speed.
摘要翻译： 车载轮廓发生器产生速度轮廓，以在从较高到较低速度限制的转变时控制车辆调速器。 计算和检查速度曲线，以确保其在有效速度限制下开始，持续降低并高于路边速度限制。 只要实际速度低于轮廓速度，调速器被修改或控制以禁止制动应用或制动应用的要求。
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公开(公告)号：US5007018A
公开(公告)日：1991-04-09
申请号：US335179
申请日：1989-04-07
CPC分类号： G06F11/10 , G06F11/076 , G06F11/0763 , G06F11/08 , G06F7/724
摘要： The invention describes a method and apparatus for effecting vital functions notwithstanding the fact that non-vital hardware is employed. A vital processor is implemented using non-vital hardware in the form of a digital computer which may for example be a microprocessor. The vital processor accepts binary input values and, based on a series of logical expressions relating output values to input values, determines the appropriate output values. Rather than employing a single bit to represent the condition of a particular input or output, unique multibit binary values or names are used. Each input or output has assigned to it at least two unique multibit values, each satisfying the code rules of a different code. Thus rather than representing a closed contact as a single 1 bit, and an open contact as a single 0 bit, in accordance with the invention the closed contact is represented by a unique multibit name which satisfies the code rules of a first code. At any point in the processing the value representing the contact can be checked to see if it satisfies the code rules, and if it does not a potential error is detected and handled. Although it is highly unlikely that a hardware failure would result in generating one of the few multibit names satisfying the code rule, that occurrence is not unlikely enough to be considered vital. Before actually controlling output devices in accordance with the processing, further tests are implemented which ensure that the multibit value computed for a particular output not only satisfies the predetermined code rule which is required, but is also correct bit for bit. Logic equations describing the relationship between output and input are actually computed using the multibit values as opposed to single bit values.
摘要翻译： 本发明描述了一种用于实现重要功能的方法和装置，尽管采用非重要硬件的事实。 使用数字计算机形式的非重要硬件实现重要的处理器，数字计算机可以是例如微处理器。 重要的处理器接受二进制输入值，并且基于将输出值与输入值相关联的一系列逻辑表达式，确定适当的输出值。 不使用单个位来表示特定输入或输出的条件，而是使用唯一的多位二进制值或名称。 每个输入或输出分配给至少两个唯一的多位值，每个值都满足不同代码的代码规则。 因此，根据本发明，根据本发明，不是将单个1位的闭合接点和作为单个0位的开放接点表示为满足第一代码的代码规则的唯一多位名称。 在处理的任何时刻，可以检查表示联系人的值，以查看它是否满足代码规则，并且如果不检测和处理潜在的错误。 尽管硬件故障极不可能导致产生满足代码规则的少数几个名称之一，但这种发生并不太可能被认为是至关重要的。 在根据处理实际控制输出设备之前，实施进一步的测试，确保为特定输出计算的多位值不仅满足所需的预定代码规则，而且还是位的正确位。 描述输出和输入之间的关系的逻辑方程实际上是使用多位值而不是单个位值来计算的。
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公开(公告)号：US4956779A
公开(公告)日：1990-09-11
申请号：US267218
申请日：1988-11-22
申请人： David B. Rutherford
发明人： David B. Rutherford
CPC分类号： B61L3/008 , B60L15/20 , B60L2200/26 , Y02T10/645 , Y02T10/7275
摘要： The functions to be performed by a digital overspeed controller are implemented by application of two concepts, namely "diverse channels" and "even/odd systems cycles"; in accordance with the first concept, two channels are maintained throughout the overspeed controller, beginning with two independent tachometer inputs; all of the functions involve operations to be performed in each of the two channels separately. The numerical results for each of the channels are different and the numerical difference between the two channels is used to prove the integrity of the functions described. The second concept of "even/odd system cycles" involves a "system cycle time", denoted T.sub.CYC, that is nominally 100 milliseconds. All of the functions of the controller are performed each system cycle. In order to be able to vitally distinguish data results between adjacent cycles, the cycles are denoted EVEN and ODD, and the results of each of the operations produce different numerical values on even and odd cycles.
摘要翻译： 由数字超速控制器执行的功能是通过应用“不同通道”和“偶数/奇数系统周期”两个概念实现的。 根据第一个概念，在整个超速控制器中保持两个通道，从两个独立的转速计输入开始; 所有功能涉及在两个通道中的每个通道中分别执行的操作。 每个通道的数值结果不同，两个通道之间的数值差异用于证明所述功能的完整性。 “偶数/奇数系统周期”的第二个概念涉及名义上为100毫秒的表示为TCYC的“系统周期时间”。 每个系统周期执行控制器的所有功能。 为了能够区分相邻周期之间的数据结果，这些周期表示为EVEN和ODD，并且每个运算的结果在偶数和奇数周期上产生不同的数值。
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7.发明授权Vital processing system adapted for the continuous verification of vital outputs from a railway signaling and control system 失效重要的处理系统适用于铁路信号和控制系统的重要输出的连续验证
公开(公告)号：US4740972A
公开(公告)日：1988-04-26
申请号：US843468
申请日：1986-03-24
CPC分类号： G06F11/08 , B61L1/20 , G06F11/0763 , G06F11/0796
摘要： Continuous verification of vital (fail-safe) outputs from an information processing system is obtained without the need for large computing capacity (overhead). Multibit test sequences are provided continuously during successive subparts of the processor system cycle to vital output interfaces which invert the bits of the signals or do not pass them depending upon the state of the output. A compiler including a random access memory (RAM) addressed by a read only memory (ROM) is configured to divide each sequence by direct and inverse polynomials on alternately occurring parts of the system cycle to provide compressed data. After each part of the system cycle, checkwords are constructed using the resultant compressed data corresponding to each output which must be proven to be in its `off` state. These checkwords are used to verify the vital operation of the system and may be applied to a vital decoder which controls the application of operating power to the output interfaces to disconnect operating power therefrom and condition the outputs to the restrictive state upon detection of a failure which may occur at any time during the entire system cycle.
摘要翻译： 获得信息处理系统的重要（故障安全）输出的连续验证，无需大的计算能力（开销）。 在处理器系统周期的连续子部分期间连续提供多比特测试序列至根据输出状态反转信号的位或不通过它们的重要输出接口。 包括由只读存储器（ROM）寻址的随机存取存储器（RAM）的编译器被配置为在系统周期的交替出现的部分上对每个序列进行直接和反向多项式的划分以提供压缩数据。 在系统周期的每个部分之后，使用对应于每个必须被证明处于“关闭”状态的输出的合成压缩数据构建检查词。 这些检查词用于验证系统的重要操作，并且可以应用于重要解码器，其控制对输出接口的操作电力的应用以断开其工作电力，并且在检测到故障时将输出调节到限制状态 可能在整个系统周期的任何时间发生。
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公开(公告)号：US4196412A
公开(公告)日：1980-04-01
申请号：US869740
申请日：1978-01-16
IPC分类号： B61L29/24 , G08G1/0967 , G08G1/02 , G08B23/00
CPC分类号： G08G1/096716 , B61L29/246 , G08G1/096758 , G08G1/096783
摘要： Apparatus for insuring a vehicle operator's attentiveness at potentially dangerous locations along a path of travel. A signalling device is provided in advance of a potentially dangerous location, in the direction of travel of the vehicle. A vehicle carried signal responsive device responds to the signalling device when within the effective zone of the signalling device. The vehicle includes warning apparatus, for example, an alarm and a buzzer. The vehicle also includes an operator actuatable push button and a speed sensing apparatus. A control device responds to the push button and to the vehicle carried signal responsive device to operate either the buzzer or the alarm. If the operator evidences his alertness to the potentially dangerous location by actuating the push button prior to reaching the signalling device (within some constraint), the control apparatus merely sounds the buzzer when the signalling device is detected and resets itself. On the other hand, if the operator fails to actuate the push button in advance of detection of the signalling device, or, if his actuation is too far in advance of detection, then the alarm is energized and will remain energized until the vehicle is brought to a stop, or a low speed, at which point, push button actuation can cancel the alarm.
摘要翻译： 用于确保车辆操作员在沿着行进路线的潜在危险位置的注意力的装置。 在潜在的危险位置之前，在车辆的行进方向上提供信号装置。 当信号装置的有效区域内时，车载信号响应装置响应信令装置。 车辆包括警报装置，例如报警器和蜂鸣器。 该车辆还包括操作者致动按钮和速度检测装置。 控制装置响应于按钮和车载信号响应装置来操作蜂鸣器或报警器。 如果操作者通过在到达信令装置之前（在一定的约束条件下）启动按钮来证明其对潜在危险位置的警觉性，则当检测到信令装置并且自动重置时，控制装置仅发出蜂鸣器。 另一方面，如果操作者在检测到信号装置之前未能按下按钮，或者如果其启动在检测之前太远，则报警器被通电并且将保持通电直到车辆被带入 停止或低速，此时按钮启动可以取消报警。
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公开(公告)号：US4365298A
公开(公告)日：1982-12-21
申请号：US146884
申请日：1980-05-05
CPC分类号： G01P3/4802 , B60K31/047 , B60T7/12
摘要： A tachometer signal provides input to first and second parallel connected channels, each of the channels comprising in series operational amplifier, threshold detector, and counting devices. A comparator checks that the same count is registered by the counters of both channels. Each of the threshold detectors is biased to require a minimum amplitude over and under tachometer pulse input in order to deliver an output to the pulse counter of the associated channel. Attenuating circuits act on the inputs of the operational amplifiers of both channels during predetermined intervals to check that the amplitude of the tachometer pulses is sufficient to be counted by the tachometer counters. Dynamic checking circuits are provided to check the integrity of the attenuating system.
摘要翻译： 转速计信号为第一和第二并联连接的通道提供输入，每个通道包括串联运算放大器，阈值检测器和计数装置。 比较器检查两个通道的计数器注册相同的计数。 每个阈值检测器被偏置以在转速计脉冲输入之上和之下需要最小幅度，以将输出传递到相关通道的脉冲计数器。 衰减电路在预定间隔期间作用于两个通道的运算放大器的输入，以检查转速计脉冲的幅度是否足以由转速计计数器计数。 提供动态检查电路以检查衰减系统的完整性。
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公开(公告)号：US5048064A
公开(公告)日：1991-09-10
申请号：US267214
申请日：1988-11-04
申请人： David B. Rutherford
发明人： David B. Rutherford
CPC分类号： G06F11/076
摘要： A vital microcompressor-based rate decoder for use in a vital processing system in on-board main line railroad and rapid transit automatic train protection systems; the design is such that a method is incorporated for tolerating specific kinds of signal disruption and in such a way that the probability of a wrongside failure has a calculable upper bound. A pickup coil transmits external or wayside signals to an arrangement which involves two channels and which provides period and duty cycle measurement of the pulses resulting from demodulation of the external signals. A counter is employed in each of the channels and a tolerance accumulation rate decoding device is included, the maximum amount of tolerance accumulated, and the minimum time required to accumulate it, being functions of the rate code selected.
摘要翻译： 一种重要的基于微压缩器的速率解码器，用于车载主线铁路和快速过境自动列车保护系统中的重要处理系统; 这种设计是为了容忍特定种类的信号中断并且以这样的方式引入了一种方法，使得错误的失败的概率具有可计算的上限。 拾取线圈将外部或路边信号传输到涉及两个通道的布置，并且其提供由外部信号的解调产生的脉冲的周期和占空比测量。 在每个通道中使用计数器，并且包括公差累积速率解码装置，累积的最大容差量和累积所需的最小时间，作为选择的速率代码的函数。
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