公开(公告)号：US20100199076A1

公开(公告)日：2010-08-05

申请号：US12639663

申请日：2009-12-16

Applicant: Dong-hoon YOO ,  Soo-jung Ryu ,  Yeon-gon Cho ,  Bernhard Egger ,  Il-hyun Park

Inventor： Dong-hoon YOO ,  Soo-jung Ryu ,  Yeon-gon Cho ,  Bernhard Egger ,  Il-hyun Park

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3879 ,  G06F9/4812

Abstract: A computing apparatus and method of handling an interrupt are provided. The computing apparatus includes a coarse-grained array, a host processor, and an interrupt supervisor. When an interrupt occurs in the coarse-grained array while performing a loop operation, the host processor processes the interrupt, and the interrupt supervisor may perform mode switching between the coarse-grained array and the host processor.

Abstract translation: 提供了一种处理中断的计算装置和方法。 计算装置包括粗粒子阵列，主处理器和中断主管。 当执行循环操作时，在粗粒度阵列中发生中断时，主机处理器处理中断，中断主管可以在粗粒度阵列与主机处理器之间执行模式切换。

公开(公告)号：US20080120493A1

公开(公告)日：2008-05-22

申请号：US11730170

申请日：2007-03-29

Applicant: Dong-Hoon Yoo ,  Soo Jung Ryu ,  Jeong-Wook Kim ,  Hong-Seok Kim ,  Hee Seok Kim

Inventor： Dong-Hoon Yoo ,  Soo Jung Ryu ,  Jeong-Wook Kim ,  Hong-Seok Kim ,  Hee Seok Kim

IPC: G06F7/38

CPC classification number: G06F8/443 ,  G06F17/5045 ,  G06F2217/68

Abstract: A profiler which provides information to optimize an application specific architecture processor and a program for the processor is provided. The profiler includes: an architecture analyzer which analyzes an architecture description, and generates architecture analysis information, the architecture description describing an architecture of an application specific architecture processor which comprises a plurality of processing elements; a static analyzer which analyzes program static information that describes static information of a program, and generates static analysis information; a dynamic analyzer which analyzes program dynamic information that describes dynamic information of the program, and generates dynamic analysis information, the dynamic information of the program being generated by simulating the program; and a cross profiling analyzer which generates information for optimizing the application specific architecture processor to implement the program based on at least one of the architecture analysis information, the static analysis information, and the dynamic analysis information.

Abstract translation: 提供了一种提供信息以优化特定于应用的架构处理器和用于处理器的程序的分析器。 分析器包括：架构分析器，其分析架构描述并生成架构分析信息，描述包括多个处理元件的应用特定架构处理器的架构的架构描述; 静态分析器，分析程序静态信息，描述程序的静态信息，并生成静态分析信息; 动态分析器，其分析描述所述程序的动态信息的程序动态信息，并且生成动态分析信息，所述程序的动态信息是通过模拟所述程序而产生的; 以及交叉分析分析器，其基于所述架构分析信息，所述静态分析信息和所述动态分析信息中的至少一个，生成用于优化所述应用专用架构处理器以实现所述程序的信息。

公开(公告)号：US09063735B2

公开(公告)日：2015-06-23

申请号：US13272846

申请日：2011-10-13

Applicant: Hee-Jin Ahn ,  Dong-Hoon Yoo ,  Bernhard Egger ,  Min-Wook Ahn ,  Jin-Seok Lee ,  Tai-Song Jin ,  Won-Sub Kim

Inventor： Hee-Jin Ahn ,  Dong-Hoon Yoo ,  Bernhard Egger ,  Min-Wook Ahn ,  Jin-Seok Lee ,  Tai-Song Jin ,  Won-Sub Kim

IPC: G06F9/38 ,  G06F9/32

CPC classification number: G06F9/325 ,  G06F9/3838 ,  G06F9/3897

Abstract: Provided are a reconfigurable processor, which is capable of reducing the probability of an incorrect computation by analyzing the dependence between memory access instructions and allocating the memory access instructions between a plurality of processing elements (PEs) based on the results of the analysis, and a method of controlling the reconfigurable processor. The reconfigurable processor extracts an execution trace from simulation results, and analyzes the memory dependence between instructions included in different iterations based on parts of the execution trace of memory access instructions.

Abstract translation: 提供了一种可重构处理器，其能够通过分析存储器访问指令之间的依赖性并且基于分析结果在多个处理元件（PE）之间分配存储器访问指令，从而降低错误计算的概率，以及 控制可重构处理器的方法。 可重配置处理器从模拟结果中提取执行跟踪，并且基于存储器访问指令的执行跟踪的部分来分析包括在不同迭代中的指令之间的存储器依赖性。

公开(公告)号：US08700887B2

公开(公告)日：2014-04-15

申请号：US12895366

申请日：2010-09-30

Applicant: Bernhard Egger ,  Dong-Hoon Yoo

Inventor： Bernhard Egger ,  Dong-Hoon Yoo

IPC: G06F9/34

CPC classification number: G06F9/30105 ,  G06F9/30014 ,  G06F9/30112 ,  G06F9/30192

Abstract: A processor and a processor control method which efficiently perform an operation on data using a register, are provided. The register may include a data type field and a data field. The processor may generate the data type bits and store the generated data type bits in the data type field.

Abstract translation: 提供了一种使用寄存器有效地对数据进行操作的处理器和处理器控制方法。 寄存器可以包括数据类型字段和数据字段。 处理器可以生成数据类型位并将生成的数据类型位存储在数据类型字段中。

公开(公告)号：US08601244B2

公开(公告)日：2013-12-03

申请号：US12706006

申请日：2010-02-16

Applicant: Bernhard Egger ,  Soo-jung Ryu ,  Dong-hoon Yoo ,  Il-hyun Park

Inventor： Bernhard Egger ,  Soo-jung Ryu ,  Dong-hoon Yoo ,  Il-hyun Park

IPC: G06F9/00

CPC classification number: G06F15/82 ,  G06F9/30072 ,  G06F9/3853

Abstract: An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein. The VLIW command includes an instruction bundle formed of a plurality of instructions to be executed in parallel and a single value indicating predicated execution, and is generated using the apparatus and method for generating a VLIW command. The VLIW processor decodes the instruction bundle and executes the instructions, which are included in the decoded instruction bundle, in parallel, according to the value indicating predicated execution.

Abstract translation: 本文提供了一种用于生成支持预定执行的非常长的指令字（VLIW）命令和用于处理VLIW的VLIW处理器和方法的装置和方法。 VLIW命令包括由并行执行的多个指令形成的指令束和指示预测执行的单个值，并且使用用于生成VLIW命令的装置和方法生成。 根据指示预先执行的值，VLIW处理器并行地解码指令束并且并行地执行包括在解码指令束中的指令。

公开(公告)号：US08495345B2

公开(公告)日：2013-07-23

申请号：US12639663

申请日：2009-12-16

Applicant: Dong-hoon Yoo ,  Soo-jung Ryu ,  Yeon-gon Cho ,  Bernhard Egger ,  Il-hyun Park

Inventor： Dong-hoon Yoo ,  Soo-jung Ryu ,  Yeon-gon Cho ,  Bernhard Egger ,  Il-hyun Park

IPC: G06F15/80

CPC classification number: G06F9/3879 ,  G06F9/4812

Abstract: A computing apparatus and method of handling an interrupt are provided. The computing apparatus includes a coarse-grained array, a host processor, and an interrupt supervisor. When an interrupt occurs in the coarse-grained array while performing a loop operation, the host processor processes the interrupt, and the interrupt supervisor may perform mode switching between the coarse-grained array and the host processor.

Abstract translation: 提供了一种处理中断的计算装置和方法。 计算装置包括粗粒子阵列，主处理器和中断主管。 当执行循环操作时，在粗粒度阵列中发生中断时，主机处理器处理中断，中断主管可以在粗粒度阵列与主机处理器之间执行模式切换。

公开(公告)号：US08490066B2

公开(公告)日：2013-07-16

申请号：US11730170

申请日：2007-03-29

Applicant: Dong-Hoon Yoo ,  Soo-Jung Ryu ,  Jeong-Wook Kim ,  Hong-Seok Kim ,  Hee Seok Kim

Inventor： Dong-Hoon Yoo ,  Soo-Jung Ryu ,  Jeong-Wook Kim ,  Hong-Seok Kim ,  Hee Seok Kim

IPC: G06F15/76 ,  G06F9/44

CPC classification number: G06F8/443 ,  G06F17/5045 ,  G06F2217/68

Abstract: A profiler which provides information to optimize an application specific architecture processor and a program for the processor is provided. The profiler includes: an architecture analyzer which analyzes an architecture description, and generates architecture analysis information, the architecture description describing an architecture of an application specific architecture processor which comprises a plurality of processing elements; a static analyzer which analyzes program static information that describes static information of a program, and generates static analysis information; a dynamic analyzer which analyzes program dynamic information that describes dynamic information of the program, and generates dynamic analysis information, the dynamic information of the program being generated by simulating the program; and a cross profiling analyzer which generates information for optimizing the application specific architecture processor to implement the program based on at least one of the architecture analysis information, the static analysis information, and the dynamic analysis information.

Abstract translation: 提供了一种提供信息以优化特定于应用的架构处理器和用于处理器的程序的分析器。 分析器包括：架构分析器，其分析架构描述并生成架构分析信息，描述包括多个处理元件的应用特定架构处理器的架构的架构描述; 静态分析器，分析程序静态信息，描述程序的静态信息，并生成静态分析信息; 动态分析器，其分析描述所述程序的动态信息的程序动态信息，并且生成动态分析信息，所述程序的动态信息是通过模拟所述程序而产生的; 以及交叉分析分析器，其基于所述架构分析信息，所述静态分析信息和所述动态分析信息中的至少一个，生成用于优化所述应用专用架构处理器以实现所述程序的信息。

公开(公告)号：US20120159114A1

公开(公告)日：2012-06-21

申请号：US13206163

申请日：2011-08-09

Applicant: Bernhard EGGER ,  Dong-Hoon Yoo ,  Won-Sub Kim

Inventor： Bernhard EGGER ,  Dong-Hoon Yoo ,  Won-Sub Kim

IPC: G06F12/10

CPC classification number: G06F9/3012 ,  G06F9/30098 ,  G06F9/30123 ,  G06F9/5077

Abstract: A register file is provided. The register file includes a plurality of registers configured to form at least one register cluster, each of the registers being configured to have a virtual index defined for each cluster and a physical index defined for each register, and an index converting unit configured to convert the virtual index to the physical index.

Abstract translation: 提供一个寄存器文件。 寄存器文件包括多个寄存器，被配置为形成至少一个寄存器簇，每个寄存器被配置为具有为每个簇定义的虚拟索引和为每个寄存器定义的物理索引，以及索引转换单元， 虚拟索引到物理索引。

公开(公告)号：US20120102496A1

公开(公告)日：2012-04-26

申请号：US13086629

申请日：2011-04-14

Applicant: Min-Wook Ahn ,  Dong-Hoon Yoo ,  Jin-Seok Lee ,  Bernhard Egger ,  Tai-Song Jin ,  Won-Sub Kim ,  Hee-Jin Ahn

Inventor： Min-Wook Ahn ,  Dong-Hoon Yoo ,  Jin-Seok Lee ,  Bernhard Egger ,  Tai-Song Jin ,  Won-Sub Kim ,  Hee-Jin Ahn

IPC: G06F9/46 ,  G06F9/38

CPC classification number: G06F9/5066

Abstract: A reconfigurable processor which merges an inner loop and an outer loop which are included in a nested loop and allocates the merged loop to processing elements in parallel, thereby reducing processing time to process the nested loop. The reconfigurable processor may extract loop execution frequency information from the inner loop and the outer loop of the nested loop, and may merge the inner loop and the outer loop based on the extracted loop execution frequency information.

Abstract translation: 一种可重构的处理器，它将包含在嵌套循环中的内循环和外循环合并，并行地将合并循环分配给处理元素，从而减少了处理嵌套循环的处理时间。 可重配置处理器可以从嵌套循环的内循环和外循环提取循环执行频率信息，并且可以基于提取的循环执行频率信息合并内循环和外循环。

公开(公告)号：US20120096247A1

公开(公告)日：2012-04-19

申请号：US13272846

申请日：2011-10-13

Applicant: Hee-Jin AHN ,  Dong-Hoon Yoo ,  Bernhard Egger ,  Min-Wook Ahn ,  Jin-Seok Lee ,  Tai-Song Jin ,  Won-Sub Kim

Inventor： Hee-Jin AHN ,  Dong-Hoon Yoo ,  Bernhard Egger ,  Min-Wook Ahn ,  Jin-Seok Lee ,  Tai-Song Jin ,  Won-Sub Kim

IPC: G06F9/32

CPC classification number: G06F9/325 ,  G06F9/3838 ,  G06F9/3897

Abstract: Provided are a reconfigurable processor, which is capable of reducing the probability of an incorrect computation by analyzing the dependence between memory access instructions and allocating the memory access instructions between a plurality of processing elements (PEs) based on the results of the analysis, and a method of controlling the reconfigurable processor. The reconfigurable processor extracts an execution trace from simulation results, and analyzes the memory dependence between instructions included in different iterations based on parts of the execution trace of memory access instructions.

Abstract translation: 提供了一种可重构处理器，其能够通过分析存储器访问指令之间的依赖性并且基于分析的结果在多个处理元件（PE）之间分配存储器访问指令，从而降低错误计算的概率，以及 控制可重构处理器的方法。 可重配置处理器从模拟结果中提取执行跟踪，并且基于存储器访问指令的执行跟踪的部分来分析包括在不同迭代中的指令之间的存储器依赖性。