公开(公告)号：US20230418469A1

公开(公告)日：2023-12-28

申请号：US18243809

申请日：2023-09-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Matthew David Pierson ,  David E. Smith ,  Timothy David Anderson

IPC: G06F3/06 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

CPC classification number: G06F3/0604 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/1668 ,  G06F13/4027 ,  G06F12/0855 ,  G06F12/0607 ,  G06F12/0828 ,  G06F12/0831 ,  G06F13/124 ,  G06F3/0607 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0815 ,  G06F12/0857 ,  G06F13/1663 ,  G06F3/0632 ,  G06F3/0673 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F9/30101 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F13/1642 ,  G06F3/064 ,  G06F9/30123 ,  G06F12/0891 ,  G06F2212/452 ,  G06F2212/657 ,  G06F2212/304 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/1016 ,  G06F12/0846

Abstract: Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.

公开(公告)号：US11822786B2

公开(公告)日：2023-11-21

申请号：US17590749

申请日：2022-02-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy David Anderson

IPC: G06F3/06 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0815 ,  G06F13/16 ,  G06F13/40 ,  G06F13/12 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891 ,  G06F12/0846 ,  G06F12/0862

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0607 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0857 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/124 ,  G06F13/1642 ,  G06F13/1663 ,  G06F13/1668 ,  G06F13/4027 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F12/0833 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0862 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1048 ,  G06F2212/304 ,  G06F2212/452 ,  G06F2212/6024 ,  G06F2212/657

Abstract: Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

公开(公告)号：US11698788B2

公开(公告)日：2023-07-11

申请号：US16805643

申请日：2020-02-28

Applicant: ADOBE INC.

Inventor： Vineet Batra ,  Ankit Phogat ,  Daniel Kaufman

IPC: G06F9/30 ,  G06F17/13 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3877 ,  G06F9/3897 ,  G06F17/13

Abstract: Systems and methods provide for efficiently and accurately determining a simplified path that conforms to the geometry of an original path by simultaneously minimizing the deviation from the original path and reducing the number of anchor points in the simplified path. A simplified path may be iteratively generated by updating parametric values and anchor points for candidate simplified paths at epochs. A deviation in distance between points on the original path and corresponding points on candidate paths may be iteratively decreased to ensure that the resulting simplified path follows the geometry of the original path to a predetermined threshold. Continuity constrains can also be applied to ensure smoothness of the simplified path.

公开(公告)号：US20180089140A1

公开(公告)日：2018-03-29

申请号：US15600508

申请日：2017-05-19

Applicant: Silicon Tailor Limited

Inventor： Paul Metzgen

IPC: G06F15/78 ,  G06F9/38 ,  G06F1/10

CPC classification number: G06F15/7867 ,  G06F1/10 ,  G06F9/3851 ,  G06F9/3869 ,  G06F9/3873 ,  G06F9/3897 ,  G06F15/7878

Abstract: A configurable processing circuit capable of handling multiple threads simultaneously, the circuit comprising a thread data store, a plurality of configurable execution units, a configurable routing network for connecting locations in the thread data store to the execution units, a configuration data store for storing configuration instances that each define a configuration of the routing network and a configuration of one or more of the plurality of execution units, and a pipeline formed from the execution units, the routing network and the thread data store that comprises a plurality of pipeline sections configured such that each thread propagates from one pipeline section to the next at each clock cycle, the circuit being configured to: (i) associate each thread with a configuration instance; and (ii) configure each of the plurality of pipeline sections for each clock cycle to be in accordance with the configuration instance associated with the respective thread that will propagate through that pipeline section during the clock cycle.

公开(公告)号：US20170351633A1

公开(公告)日：2017-12-07

申请号：US15173859

申请日：2016-06-06

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Wei Xiang Goh

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F9/3885 ,  G06F9/3897 ,  G06F13/4068

Abstract: A method, a computing system, and a non-transitory machine readable storage medium containing instructions for managing a stream processing topology are provided. In an example, the method includes receiving a first topology that communicatively couples a plurality of processing elements via a first arrangement of interconnections to perform an operation on a stream of data. A second topology is defined that communicatively couples the plurality of processing elements via a second arrangement of interconnections that is different from the first arrangement. The second topology assigns the plurality of processing elements a first set of operations. The second topology is provided to a stream processing manager and is modified during processing of the stream of data by assigning a second set of operations to the plurality of processing elements that is different from the first set of operations.

公开(公告)号：US09798551B2

公开(公告)日：2017-10-24

申请号：US15081203

申请日：2016-03-25

Applicant: Intel Corporation

Inventor： Scott Krig ,  Teresa Morrison

IPC: G06F9/38 ,  G06F15/78 ,  G06F9/30

CPC classification number: G06F9/5027 ,  G06F9/30079 ,  G06F9/30083 ,  G06F9/3867 ,  G06F9/3873 ,  G06F9/3897 ,  G06F9/5094 ,  G06F15/7839 ,  G06F15/7867 ,  G06F15/8007

Abstract: A method and apparatus for providing a scalable compute fabric are provided herein. The method includes determining a workflow for processing by the scalable compute fabric, wherein the workflow is based on an instruction set. A pipeline in configured dynamically for processing the workflow, and the workflow is executed using the pipeline.

公开(公告)号：US20170039070A1

公开(公告)日：2017-02-09

申请号：US15297885

申请日：2016-10-19

Applicant: INTEL CORPORATION

Inventor： NATHAN D. DAUTENHAHN ,  JUSTIN GOTTSCHLICH ,  GILLES POKAM ,  CRISTIANO PEREIRA ,  SHILIANG HU ,  KLAUS DANNE ,  ROLF KASSA

IPC: G06F9/30 ,  G06F11/36

CPC classification number: G06F9/30145 ,  G06F9/3009 ,  G06F9/3895 ,  G06F9/3897 ,  G06F9/52 ,  G06F11/0724 ,  G06F11/1438 ,  G06F11/1484 ,  G06F11/3636

Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.

Abstract translation: 描述了根据一个实施例的用于促进软件程序中的指令原子性违规的动态和有效管理的机制。 如本文所述的实施例的方法包括在来自记录系统的重放逻辑处接收运行第一宏指令的第一软件线程的记录和运行第二宏指令的第二软件线程。 第一软件线程和第二软件线程分别由计算设备处理器的第一核心和第二核心执行。 记录系统可以记录第一和第二宏指令之间的交织。 该方法包括在发生时准确地重播第一和第二宏指令的交错记录。 正确重放可以包括重播第一和第二宏指令的本地存储器状态以及第一和第二软件线程的全局存储器状态。

公开(公告)号：US09519486B1

公开(公告)日：2016-12-13

申请号：US13683720

申请日：2012-11-21

Applicant: Xilinx, Inc.

Inventor： Michaela Blott ,  Thomas B. English ,  Kornelis A. Vissers

IPC: G06F13/00 ,  G06F9/38 ,  G06F15/78 ,  H03K19/177

CPC classification number: G06F9/3867 ,  G06F9/3897 ,  G06F15/7867 ,  G06F15/7878 ,  H03K19/17752 ,  H03K19/17756

Abstract: A method of processing data in an integrated circuit is described. The method comprises establishing a pipeline of processing blocks, wherein each processing block has a different function; coupling a data packet having data and meta-data to an input of the pipeline of processing blocks; and processing the data of the data packet using predetermined processing blocks based upon the meta-data. A device for processing data in an integrated circuit is also described.

Abstract translation: 描述了一种在集成电路中处理数据的方法。 该方法包括建立处理块流水线，其中每个处理块具有不同的功能; 将具有数据和元数据的数据分组耦合到处理块的流水线的输入; 以及使用基于所述元数据的预定处理块来处理所述数据分组的数据。 还描述了用于处理集成电路中的数据的装置。

公开(公告)号：US09501340B2

公开(公告)日：2016-11-22

申请号：US13977690

申请日：2013-03-15

Applicant: Nathan D. Dautenhahn ,  Justin E. Gottschlich ,  Gilles Pokam ,  Cristiano L. Pereira ,  Shiliang Hu ,  Klaus Danne ,  Rolf Kassa

Inventor： Nathan D. Dautenhahn ,  Justin E. Gottschlich ,  Gilles Pokam ,  Cristiano L. Pereira ,  Shiliang Hu ,  Klaus Danne ,  Rolf Kassa

IPC: G06F9/45 ,  G06F11/07 ,  G06F9/38 ,  G06F11/14

CPC classification number: G06F9/30145 ,  G06F9/3009 ,  G06F9/3895 ,  G06F9/3897 ,  G06F9/52 ,  G06F11/0724 ,  G06F11/1438 ,  G06F11/1484 ,  G06F11/3636

Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.

Abstract translation: 描述了根据一个实施例的用于促进软件程序中的指令原子性违规的动态和有效管理的机制。 如本文所述的实施例的方法包括在来自记录系统的重放逻辑处接收运行第一宏指令的第一软件线程的记录和运行第二宏指令的第二软件线程。 第一软件线程和第二软件线程分别由计算设备处理器的第一核心和第二核心执行。 记录系统可以记录第一和第二宏指令之间的交织。 该方法包括在发生时准确地重播第一和第二宏指令的交错记录。 正确重放可以包括重播第一和第二宏指令的本地存储器状态以及第一和第二软件线程的全局存储器状态。

公开(公告)号：US09465620B2

公开(公告)日：2016-10-11

申请号：US13721400

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Scott Krig ,  Teresa Morrison

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/78

CPC classification number: G06F9/5027 ,  G06F9/30079 ,  G06F9/30083 ,  G06F9/3867 ,  G06F9/3873 ,  G06F9/3897 ,  G06F9/5094 ,  G06F15/7839 ,  G06F15/7867 ,  G06F15/8007

Abstract: A method and apparatus for providing a scalable compute fabricare provided herein. The method includes determining a workflow for processing by the scalable compute fabric, wherein the workflow is based on an instruction set. A pipeline in configured dynamically for processing the workflow, and the workflow is executed using the pipeline.

Abstract translation: 本文提供了一种用于提供可扩展计算结构的方法和装置。 该方法包括确定由可伸缩计算结构进行处理的工作流，其中工作流基于指令集。 管道配置为动态处理工作流程，并使用流水线执行工作流程。