公开(公告)号：US06911369B2

公开(公告)日：2005-06-28

申请号：US10365257

申请日：2003-02-12

Applicant: Kuen-Chyr Lee ,  Liang-Gi Yao ,  Fu Chin Yang ,  Shih-Chang Chen ,  Mong-Song Liang

Inventor： Kuen-Chyr Lee ,  Liang-Gi Yao ,  Fu Chin Yang ,  Shih-Chang Chen ,  Mong-Song Liang

IPC: H01L21/20 ,  H01L21/205 ,  H01L21/3205 ,  H01L21/331 ,  H01L21/762

CPC classification number: H01L21/32055 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/76232 ,  H01L29/66242

Abstract: The present disclosure provides a process for producing a SiGe layer in a bipolar device having a reduced amount of gaps or discontinuities on a shallow trench isolation (STI) region use for a base electrode connection. The process is used for forming an SiGe layer for use in a semiconductor device. The process includes doping a single crystal substrate with a first dopant type, baking the doped single crystal substrate at a temperature less than 900° C., and at a pressure less than 100 torr; and depositing the SiGe layer on the baked single crystal substrate (epi SiGe) to serve as the base electrode and on the STI region (poly SiGe) to serve as a connection for the base electrode. The semiconductor device is thereby created from the combination of the doped single crystal substrate and the deposited SiGe layer.

Abstract translation: 本公开提供了一种用于在双极性器件中制造SiGe层的方法，该双极器件在用于基极连接的浅沟槽隔离（STI）区域上具有减少的间隙或不连续性。 该方法用于形成用于半导体器件的SiGe层。 该方法包括掺杂具有第一掺杂剂类型的单晶衬底，在小于900℃的温度和低于100托的压力下烘焙掺杂的单晶衬底; 以及将SiGe层沉积在焙烧的单晶衬底（epi SiGe）上以用作基极和在STI区（poly SiGe）上作为基极的连接。 由此，由掺杂的单晶衬底和沉积的SiGe层的组合形成半导体器件。