公开(公告)号：US12106960B2

公开(公告)日：2024-10-01

申请号：US17504391

申请日：2021-10-18

申请人： Analog Devices, Inc.

发明人： James G. Fiorenza ,  Daniel Piedra

IPC分类号： H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L21/02694 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

摘要： Electric field management techniques in GaN based semiconductors that utilize patterned regions of differing conductivity under the active GaN device, such as a GaN high electron mobility transistor (HEMT), are described. As an example, a patterned layer of oxidized silicon can be formed superjacent a layer of silicon dioxide during or prior to the heteroepitaxy of GaN or another semiconductor material. These techniques can be useful for back-side electric field management because a silicon layer, for example, can be made conductive to act as a back-side field plate.

公开(公告)号：US12040184B2

公开(公告)日：2024-07-16

申请号：US17145499

申请日：2021-01-11

申请人： ASM IP Holding B.V.

发明人： David Kohen ,  Harald Benjamin Profijt ,  Andrew Kretzschmar

IPC分类号： H01L29/10 ,  H01L21/02 ,  H01L29/165 ,  H10B43/27

CPC分类号： H01L21/0245 ,  H01L21/02164 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L29/165 ,  H10B43/27 ,  H01L29/1054

摘要： A method for forming a forming a semiconductor structure is disclosed. The method may include: forming a silicon oxide layer on a surface of a substrate, depositing a silicon germanium (Si1-xGex) seed layer directly on the silicon oxide layer, and depositing a germanium (Ge) layer directly on the silicon germanium (Si1-xGex) seed layer. Semiconductor structures including a germanium (Ge) layer deposited on silicon oxide utilizing an intermediate silicon germanium (Si1-xGex) seed layer are also disclosed.

公开(公告)号：US20240153762A1

公开(公告)日：2024-05-09

申请号：US18283728

申请日：2022-03-11

申请人： Paragraf Limited

发明人： Sebastian DIXON ,  Jaspreet KAINTH ,  Robert JAGT

IPC分类号： H01L21/02

CPC分类号： H01L21/02527 ,  H01L21/02008 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/02488 ,  H01L21/02502

摘要： A wafer for the CVD growth of uniform graphene and method of manufacture thereof There is provided a wafer for the CVD growth of uniform graphene at a temperature in excess of 700° C., the wafer comprising in order: a planar silicon substrate, an insulating layer provided across the silicon substrate, and a barrier layer provided across the insulating layer, wherein the insulating layer is a silicon nitride and/or aluminium nitride layer, and wherein the barrier layer has a constant thickness of 50 nm or less and provides a growth surface for the CVD growth of uniform graphene.

公开(公告)号：US11978784B2

公开(公告)日：2024-05-07

申请号：US17985112

申请日：2022-11-10

申请人： Intel Corporation

发明人： Cory Bomberger ,  Anand Murthy ,  Susmita Ghose ,  Zachary Geiger

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/34 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/6681 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/34 ,  H01L29/6653 ,  H01L29/7848 ,  H01L29/7853 ,  H01L21/02502 ,  H01L29/42392

摘要： Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US20240136441A1

公开(公告)日：2024-04-25

申请号：US18164600

申请日：2023-02-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ken-Ichi Goto ,  Cheng-Yi Wu

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L29/04 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/78684 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02565 ,  H01L21/02598 ,  H01L21/02609 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1229 ,  H01L27/1237 ,  H01L29/045 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/18

摘要： A semiconductor device includes a substrate, and a first transistor disposed on the substrate. The first transistor includes a first channel layer, a magnesium oxide layer, a first gate electrode, a first gate dielectric and first source/drain electrodes. A crystal orientation of the first channel layer is or . The magnesium oxide layer is located below the first channel layer and in contact with the first channel layer. The first gate electrode is located over the first channel layer. The first gate dielectric is located in between the first channel layer and the first gate electrode. The first source/drain electrodes are disposed on the first channel layer.

公开(公告)号：US11923195B2

公开(公告)日：2024-03-05

申请号：US17352851

申请日：2021-06-21

申请人： SAMSUNG ELECTRONICS CO., LTD. ,  iBeam Materials, Inc.

发明人： Junhee Choi ,  Vladmir Matias ,  Joohun Han

IPC分类号： H01L21/02

CPC分类号： H01L21/02502 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02496 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02516 ,  H01L21/02598 ,  H01L21/02192 ,  H01L21/02266 ,  H01L21/02422 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02631

摘要： A single crystal semiconductor includes a strain compensation layer; an amorphous substrate disposed on the strain compensation layer; a lattice matching layer disposed on the amorphous substrate and including two or more single crystal layers; and a single crystal semiconductor layer disposed on the lattice matching layer, the lattice matching layer including a direction control film disposed on the amorphous substrate and including a single crystal structure, and a buffer layer including a material different from that of the direction control film, the buffer layer being disposed on the direction control film and including a single crystal structure.

公开(公告)号：US20240071756A1

公开(公告)日：2024-02-29

申请号：US18494122

申请日：2023-10-25

申请人： SUMCO CORPORATION

发明人： Koji MATSUMOTO ,  Toshiaki ONO ,  Hiroshi AMANO ,  Yoshio HONDA

IPC分类号： H01L21/02 ,  H01L21/322

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/3221 ,  H01L21/02664

摘要： A method for manufacturing a group III nitride semiconductor substrate, that includes: growing a first AlN buffer layer on an Si substrate at a first growth temperature; growing a second AlN buffer layer on the first AlN buffer layer at a second growth temperature higher than the first growth temperature; and growing a group III nitride semiconductor layer on the second AlN buffer layer, wherein an Al raw material and an N raw material are alternately repeatedly fed in the growing the first AlN buffer layer.

公开(公告)号：US11854802B2

公开(公告)日：2023-12-26

申请号：US17299954

申请日：2020-04-03

申请人： Suzhou Institute of Nano-Tech and Nano-Bionics (Sinano), Chinese Academy of Sciences

发明人： Yukun Zhao ,  Shulong Lu ,  Zhiwei Xing ,  Jianya Zhang

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L21/0259 ,  H01L29/66522 ,  H01L29/7842 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02603

摘要： The present invention discloses a super-flexible transparent semiconductor film and a preparation method thereof, the method includes: providing an epitaxial substrate; growing a sacrificial layer on the epitaxial substrate; stacking and growing at least one layer of Al1-nGanN epitaxial layer on the sacrificial layer, wherein 0

公开(公告)号：US11764059B2

公开(公告)日：2023-09-19

申请号：US17014272

申请日：2020-09-08

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Johji Nishio ,  Tatsuo Shimizu

IPC分类号： H01L21/02 ,  H01L21/66 ,  H01L29/16 ,  H01L21/04 ,  H01L29/06 ,  H01L29/78 ,  H01L29/167 ,  H01L29/872 ,  H01L29/739

CPC分类号： H01L21/02634 ,  H01L21/0262 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02502 ,  H01L21/02529 ,  H01L21/0475 ,  H01L22/20 ,  H01L29/0684 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/872

摘要： According to one embodiment, a method for manufacturing a substrate is disclosed. The method can include preparing a structure body. The structure body includes a first semiconductor member and a second semiconductor member. The first semiconductor member includes silicon carbide including a first element. The second semiconductor member includes silicon carbide including a second element. The first element includes at least one selected from a first group consisting of N, P, and As. The second element includes at least one selected from a second group consisting of B, Al, and Ga. The method can include forming a hole that extends through the second semiconductor member and reaches the first semiconductor member. In addition, the method can include forming a third semiconductor member in the hole. The third semiconductor member includes silicon carbide including a third element. The third element includes at least one selected from the first group.

公开(公告)号：US20230231051A1

公开(公告)日：2023-07-20

申请号：US17672733

申请日：2022-02-16

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Jhe Hsu ,  Che-Yi Ho

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02

CPC分类号： H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639

摘要： A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, a second buffer layer on the first buffer layer, a bulk layer on the second buffer layer, a first cap layer on the bulk layer, and a second cap layer on the first cap layer. Preferably, the bottom surface of the first buffer layer includes a linear surface, a bottom surface of the second buffer layer includes a curve, and the second buffer layer includes a linear sidewall.