公开(公告)号：US20060244856A1

公开(公告)日：2006-11-02

申请号：US11380544

申请日：2006-04-27

Applicant: Hiroyasu Tagami ,  Masahiro Inoue ,  Hideki Yamamoto

Inventor： Hiroyasu Tagami ,  Masahiro Inoue ,  Hideki Yamamoto

IPC: H04N5/335

CPC classification number: H04N5/335

Abstract: A horizontal register transfer pulse generator includes: phase adjuster generating an output signal, from reference signal; and horizontal blanking period generator based on output signal, reference signal, and horizontal blanking pulse, wherein horizontal blanking period generator includes: delay masking pulse generator generating delay masking pulse delayed by predetermined phase relative to masking pulse generated on horizontal blanking pulse inputted into horizontal blanking period generator; and determination means determining phase difference between output signal and reference signal, when phase difference between output signal and reference signal is less than predetermined phase, horizontal blanking period generator combines masking pulse with output signal to generate horizontal register transfer pulse with horizontal blanking period, and when phase difference between output signal and reference signal is equal to or greater than predetermined phase, horizontal blanking period generator combines delay masking pulse with output signal to generate horizontal register transfer pulse with horizontal blanking period.

Abstract translation: 水平寄存器传送脉冲发生器包括：相位调节器，从参考信号产生输出信号; 基于输出信号，参考信号和水平消隐脉冲的水平消隐周期发生器，其中水平消隐周期发生器包括：延迟屏蔽脉冲发生器产生延迟预定相位相对于输入到水平消隐的水平消隐脉冲上产生的屏蔽脉冲的延迟屏蔽脉冲 周期发生器; 以及当输出信号和参考信号之间的相位差小于预定相位时，决定装置确定输出信号和参考信号之间的相位差，水平消隐周期发生器将屏蔽脉冲与输出信号组合，以产生具有水平消隐周期的水平寄存器传送脉冲，以及 当输出信号和参考信号之间的相位差等于或大于预定相位时，水平消隐周期发生器将延迟屏蔽脉冲与输出信号组合，以产生具有水平消隐周期的水平寄存器传送脉冲。

公开(公告)号：US20060028566A1

公开(公告)日：2006-02-09

申请号：US11179960

申请日：2005-07-12

Applicant: Takashi Shimono ,  Hiroyasu Tagami

Inventor： Takashi Shimono ,  Hiroyasu Tagami

IPC: H04N5/335

CPC classification number: H04N5/335

Abstract: Disclosed herein is a timing signal generating circuit including, a memory for storing rising edge position data and falling edge position data of pulses of a timing signal to be generated, and a pulse generator for generating the timing signal on a basis of the rising edge position data and the falling edge position data, wherein the memory stores pulse count data indicating a number of pulses of the timing signal, and the pulse generator includes rising edge signal generating circuits for generating rising edge signals on a basis of respective pieces of the rising edge position data, falling edge signal generating circuits for generating falling edge signals on a basis of respective pieces of the falling edge position data, an active control circuit for setting in an active state the rising edge signals and the falling edge signals generated by the rising edge signal generating circuits and the falling edge signal generating circuits that correspond in number to the pulse count data, and a pulse generating circuit for generating the timing signal on a basis of the rising edge signals and the falling edge signals set in the active state by the active control circuit.

Abstract translation: 这里公开了一种定时信号发生电路，包括：存储器，用于存储要产生的定时信号的脉冲的上升沿位置数据和下降沿位置数据;以及脉冲发生器，用于基于上升沿位置产生定时信号 数据和下降沿位置数据，其中存储器存储指示定时信号的脉冲数的脉冲计数数据，并且脉冲发生器包括用于基于各个上升沿产生上升沿信号的上升沿信号生成电路 位置数据，下降沿信号生成电路，用于基于各个下降沿位置数据产生下降沿信号;有源控制电路，用于将上升沿信号和由上升沿产生的下降沿信号设置为有效状态 信号发生电路和数字对应于脉冲计数数据的下降沿信号发生电路， 以及脉冲发生电路，用于根据由有源控制电路设置在激活状态中的上升沿信号和下降沿信号产生定时信号。

公开(公告)号：US20130049760A1

公开(公告)日：2013-02-28

申请号：US13592436

申请日：2012-08-23

Applicant: Kazutoshi Ono ,  Naoto Yanase ,  Hiroyasu Tagami ,  Nobuhiko Shigyo ,  Toshio Suzuki ,  Kouzi Tsukamoto

Inventor： Kazutoshi Ono ,  Naoto Yanase ,  Hiroyasu Tagami ,  Nobuhiko Shigyo ,  Toshio Suzuki ,  Kouzi Tsukamoto

IPC: H03K17/687 ,  G01N27/416

CPC classification number: H01M10/482 ,  H02J7/0021 ,  H03K17/102 ,  H03K2217/0009 ,  H03K2217/0018

Abstract: Disclosed herein is a switch for turning on/off the connection between a first terminal and a second terminal. The switch includes a first transistor circuit configured from two transistors connected in series between the first terminal and the second terminal; and a second transistor circuit having a gate terminal connected to source terminals of the two transistors and a source terminal connected to gate terminals of the two transistors. The connection between the first terminal and the second terminal is changed over between on and off states by changing over a potential to the source terminal of the second transistor circuit between high and low levels.

Abstract translation: 这里公开了用于打开/关闭第一端子和第二端子之间的连接的开关。 开关包括由串联连接在第一端子和第二端子之间的两个晶体管构成的第一晶体管电路; 以及具有连接到两个晶体管的源极端子的栅极端子和与两个晶体管的栅极端子连接的源极端子的第二晶体管电路。 通过在第二晶体管电路的高电平和低电平之间切换到第二晶体管电路的源极的电位，第一端子和第二端子之间的连接在导通和截止状态之间切换。

公开(公告)号：US20100271529A1

公开(公告)日：2010-10-28

申请号：US12777372

申请日：2010-05-11

Applicant: Takashi Shimono ,  Hiroyasu Tagami

Inventor： Takashi Shimono ,  Hiroyasu Tagami

IPC: H04N5/335

CPC classification number: H03K3/84 ,  H03K7/04 ,  H04N5/3577 ,  H04N5/3728 ,  H04N5/3765

Abstract: A transfer pulse generator circuit for outputting a vertical register transfer pulse includes transfer pulse control circuit for controlling to set rise and fall timings of the vertical register transfer pulse to desired timings in a predetermined period.

Abstract translation: 用于输出垂直寄存器传送脉冲的传送脉冲发生器电路包括传送脉冲控制电路，用于控制在预定时间段内将垂直寄存器传送脉冲的上升和下降定时设置为期望的定时。