公开(公告)号：US08656376B2

公开(公告)日：2014-02-18

申请号：US13223489

申请日：2011-09-01

Applicant: Jenq Kuen Lee ,  Chi Bang Kuan

Inventor： Jenq Kuen Lee ,  Chi Bang Kuan

IPC: G06F15/00 ,  G06F15/76 ,  G06F9/30 ,  G06F9/40 ,  G06F9/44 ,  G06F9/45

CPC classification number: G06F8/441 ,  G06F9/3012 ,  G06F9/3891

Abstract: A method for providing intrinsic supports for a VLIW DSP processor with distributed register files comprises the steps of: generating a program representation with cluster information on instructions of the DSP processor, wherein the cluster information is provided by a program with cluster intrinsic coding; identifying data stream operations indicating parallel instruction sequences applied on different data sets in the program representation; identifying data sharing relations indicating data shared by the data stream operations in the program representation; identifying data aggregation relations indicating results aggregated from the data stream operations in the program representation; and performing register allocation for the DSP processor according to the identified data stream operations, the data sharing relations and the data aggregation relations.

Abstract translation: 一种用于为具有分布式寄存器文件的VLIW DSP处理器提供固有支持的方法包括以下步骤：根据DSP处理器的指令生成具有簇信息的程序表示，其中所述簇信息由具有簇固有编码的程序提供; 识别在程序表示中指示应用于不同数据集合上的并行指令序列的数据流操作; 识别指示由节目表示中的数据流操作共享的数据的数据共享关系; 识别指示从节目表示中的数据流操作聚合的结果的数据聚合关系; 并根据识别的数据流操作，数据共享关系和数据聚合关系为DSP处理器执行寄存器分配。

公开(公告)号：US08407715B2

公开(公告)日：2013-03-26

申请号：US11742322

申请日：2007-04-30

Applicant: Jenq Kuen Lee ,  Kun Yuan Hsieh ,  Yung Chia Lin

Inventor： Jenq Kuen Lee ,  Kun Yuan Hsieh ,  Yung Chia Lin

IPC: G06F9/46 ,  G06F7/38

CPC classification number: G06F9/3012 ,  G06F9/30123 ,  G06F9/462

Abstract: A method of optimizing multi-set context switch for embedded processors includes the steps of partitioning a plurality of registers into a plurality of register sets based on a live-range-sensitive context-switch procedure that is associated with a usage frequency of each of the registers, storing contents of first target registers according to live set information of a current task, wherein the first target registers are selected from the register sets, determining a next task by an operating system and updating the live set information according to the next task, and restoring contents of second target registers according to the updated live set information, wherein the second target registers are selected from the register sets.

Abstract translation: 一种优化用于嵌入式处理器的多集上下文切换的方法包括以下步骤：基于与每个的每个的使用频率相关联的实时范围敏感的上下文切换过程将多个寄存器分割成多个寄存器集 寄存器，根据当前任务的实时设置信息存储第一目标寄存器的内容，其中从寄存器集中选择第一目标寄存器，由操作系统确定下一任务，并根据下一任务更新实时集信息， 以及根据更新的实时集合信息恢复第二目标寄存器的内容，其中从寄存器集中选择第二目标寄存器。

公开(公告)号：US20130024666A1

公开(公告)日：2013-01-24

申请号：US13184857

申请日：2011-07-18

Applicant: JENQ KUEN LEE ,  YU TE LIN ,  CHUNG JU WU

Inventor： JENQ KUEN LEE ,  YU TE LIN ,  CHUNG JU WU

IPC: G06F9/312

CPC classification number: G06F9/3012 ,  G06F9/3836 ,  G06F9/3891

Abstract: A method of scheduling a plurality of instructions for a processor comprises the steps of: establishing a functional unit resource table comprising a plurality of columns, each of which corresponds to one of a plurality of operation cycles of the processor and comprises a plurality of fields, each of which indicates a functional unit of the processor; establishing a ping-pong resource table comprising a plurality of columns, each of which corresponds to one of the plurality of operation cycles of the processor and comprises a plurality of fields, each of which indicates a read port or a write port of a register bank of the processor; and allotting the plurality of instructions to the plurality of operation cycles of the processor and registering the functional units and the ports of the register banks corresponding to the allotted instructions on the functional unit resource table and the ping-pong resource table.

Abstract translation: 一种为处理器调度多个指令的方法包括以下步骤：建立包括多个列的功能单元资源表，每个列对应于处理器的多个操作周期中的一个，并且包括多个字段， 其中的每一个表示处理器的功能单元; 建立包括多个列的乒乓资源表，每个列对应于处理器的多个操作周期中的一个，并且包括多个字段，每个字段指示寄存器组的读端口或写端口 的处理器; 以及将所述多个指令分配给所述处理器的所述多个操作周期，并且将对应于所述分配指令的所述寄存器组的功能单元和端口注册在所述功能单元资源表和所述乒乓资源表上。

公开(公告)号：US20120159110A1

公开(公告)日：2012-06-21

申请号：US12974291

申请日：2010-12-21

Applicant: CHUNG JU WU ,  YU TE LIN ,  JENQ KUEN LEE

Inventor： CHUNG JU WU ,  YU TE LIN ,  JENQ KUEN LEE

IPC: G06F12/02

CPC classification number: G06F9/3891

Abstract: A method of allocating registers for a processor based on cycle information is disclosed. The processor comprises a first cluster and a second cluster. Each cluster comprises a first functional unit, a second functional unit, a first local register file connected to the first functional unit, a second local register file connected to the second register file, and a global register file having a ping-pong structure formed by a first register bank and a second register bank. After building a Component/Register Type Associated Data Dependency Graph (CRTA-DDG), a functional unit assignment, register file assignment, ping-pong register bank assignment, and cluster assignment are performed to take full advantage of the properties of a processor as well as cycle information.

Abstract translation: 公开了一种基于周期信息为处理器分配寄存器的方法。 处理器包括第一集群和第二集群。 每个集群包括第一功能单元，第二功能单元，连接到第一功能单元的第一本地寄存器文件，连接到第二寄存器堆的第二本地寄存器文件，以及具有乒乓结构的全局寄存器堆，所述乒乓结构由 第一个注册银行和第二个注册银行。 在构建组件/寄存器类型相关数据依赖关系图（CRTA-DDG）之后，执行功能单元分配，寄存器文件分配，乒乓寄存器组分配和集群分配，以充分利用处理器的属性 作为循环信息。

公开(公告)号：US20080270771A1

公开(公告)日：2008-10-30

申请号：US11742322

申请日：2007-04-30

Applicant: Jenq Kuen Lee ,  Kun Yuan Hsieh ,  Yung Chia Lin

Inventor： Jenq Kuen Lee ,  Kun Yuan Hsieh ,  Yung Chia Lin

IPC: G06F9/312

CPC classification number: G06F9/3012 ,  G06F9/30123 ,  G06F9/462

Abstract: A method of optimizing multi-set context switch for embedded processors includes the steps of partitioning a plurality of registers into a plurality of register sets based on a live-range-sensitive context-switch procedure that is associated with a usage frequency of each of the registers, storing contents of first target registers according to live set information of a current task, wherein the first target registers are selected from the register sets, determining a next task by an operating system and updating the live set information according to the next task, and restoring contents of second target registers according to the updated live set information, wherein the second target registers are selected from the register sets.

Abstract translation: 一种优化用于嵌入式处理器的多集上下文切换的方法包括以下步骤：基于与每个的每个的使用频率相关联的实时范围敏感的上下文切换过程将多个寄存器分割成多个寄存器集 寄存器，根据当前任务的实时设置信息存储第一目标寄存器的内容，其中从寄存器集中选择第一目标寄存器，由操作系统确定下一任务，并根据下一任务更新实时集信息， 以及根据更新的实时集合信息恢复第二目标寄存器的内容，其中从寄存器集中选择第二目标寄存器。

公开(公告)号：US08539462B2

公开(公告)日：2013-09-17

申请号：US12974291

申请日：2010-12-21

Applicant: Chung Ju Wu ,  Yu Te Lin ,  Jenq Kuen Lee

Inventor： Chung Ju Wu ,  Yu Te Lin ,  Jenq Kuen Lee

IPC: G06F9/45

CPC classification number: G06F9/3891

Abstract: A method of allocating registers for a processor based on cycle information is disclosed. The processor comprises a first cluster and a second cluster. Each cluster comprises a first functional unit, a second functional unit, a first local register file connected to the first functional unit, a second local register file connected to the second register file, and a global register file having a ping-pong structure formed by a first register bank and a second register bank. After building a Component/Register Type Associated Data Dependency Graph (CRTA-DDG), a functional unit assignment, register file assignment, ping-pong register bank assignment, and cluster assignment are performed to take full advantage of the properties of a processor as well as cycle information.

Abstract translation: 公开了一种基于周期信息为处理器分配寄存器的方法。 处理器包括第一集群和第二集群。 每个集群包括第一功能单元，第二功能单元，连接到第一功能单元的第一本地寄存器文件，连接到第二寄存器堆的第二本地寄存器文件，以及具有乒乓结构的全局寄存器堆，所述乒乓结构由 第一个注册银行和第二个注册银行。 在构建组件/寄存器类型关联数据依赖图（CRTA-DDG）之后，执行功能单元分配，寄存器文件分配，乒乓寄存器组分配和集群分配，以充分利用处理器的属性 作为循环信息。

公开(公告)号：US08239560B2

公开(公告)日：2012-08-07

申请号：US11864147

申请日：2007-09-28

Applicant: Jenq Kuen Lee ,  Chung Kai Chen ,  Yu Hao Chang ,  Chih Chieh Yang ,  Kai Hsin Chung

Inventor： Jenq Kuen Lee ,  Chung Kai Chen ,  Yu Hao Chang ,  Chih Chieh Yang ,  Kai Hsin Chung

IPC: G06F15/16

CPC classification number: H04L65/605 ,  H04L29/06027 ,  H04L65/4084

Abstract: A system of remote objects with network streaming ability includes a streaming client, a plurality of streaming servers, a streaming buffer area, a plurality of first continuous buffer areas, a streaming controller, a plurality of first network connections, and a plurality of second network connections. The plurality of streaming servers is used to respond a remote procedure call from the streaming client. The streaming buffer area stores a complete data unit for the streaming client to access. A generation method of remote objects with network streaming ability is further provided. The method includes executing a link procedure, executing a streaming preparation, executing a streaming transfer procedure, and closing the link procedure.

Abstract translation: 具有网络流传输能力的远程对象的系统包括流客户端，多个流服务器，流缓冲区，多个第一连续缓冲区，流控制器，多个第一网络连接和多个第二网络 连接。 多个流服务器用于响应来自流客户端的远程过程调用。 流缓冲区存储用于流客户端访问的完整数据单元。 进一步提供具有网络流能力的远程对象的生成方法。 该方法包括执行链接过程，执行流媒体准备，执行流传输过程和关闭链接过程。

公开(公告)号：US08200944B2

公开(公告)日：2012-06-12

申请号：US12490932

申请日：2009-06-24

Applicant: Jenq Kuen Lee ,  Ling Hua Tseng ,  Chung Kai Chen

Inventor： Jenq Kuen Lee ,  Ling Hua Tseng ,  Chung Kai Chen

IPC: G06F9/30 ,  G06F9/40

CPC classification number: G06F9/3012 ,  G06F8/441 ,  G06F9/3885 ,  G06F9/3891

Abstract: A method for pipelining instructions on a PAC processor includes determining a minimum initial interval, and grouping the instructions so that the operands of dependent instructions are assigned to the same local register file. The virtual registers of the instructions that have data dependency across the first functional unit and the second functional unit are assigned to a global register file. The instructions are then modulo scheduled based on a current value of initial interval. The virtual registers of the scheduled instructions are allocated to the corresponding register files. If the allocation fails, a set of virtual registers is transferred from the first or second register file to the global register file.

Abstract translation: 用于在PAC处理器上流水线指令的方法包括确定最小初始间隔，并对指令进行分组，使得依赖指令的操作数被分配给相同的本地寄存器文件。 在第一功能单元和第二功能单元之间具有数据依赖性的指令的虚拟寄存器被分配给全局寄存器文件。 然后根据初始间隔的当前值对指令进行模数调度。 调度指令的虚拟寄存器被分配给相应的寄存器文件。 如果分配失败，则一组虚拟寄存器从第一或第二寄存器文件传输到全局寄存器文件。

公开(公告)号：US08051411B2

公开(公告)日：2011-11-01

申请号：US11835828

申请日：2007-08-08

Applicant: Jenq Kuen Lee ,  Chung Ju Wu ,  Sheng Yuan Chen

Inventor： Jenq Kuen Lee ,  Chung Ju Wu ,  Sheng Yuan Chen

IPC: G06F9/45 ,  G06F9/445

CPC classification number: G06F9/3885 ,  G06F8/443 ,  G06F9/3012 ,  G06F9/3828 ,  G06F9/3891

Abstract: A method for copy propagations of a processor including two clusters, each cluster comprising a first function unit and a second function unit, a first local register file and a second local register file being respectively accessible by the first and second function unit only, and a global register file having a ping-pong structure to access the first and second local register files, the method comprising the steps of: (a) listing possible copy propagation paths between two nodes of a data flow graph; (b) calculating a profit of machine cycles for each of the copy propagation paths according to constraints of the processor; and (c) performing a copy propagation through the copy propagation path if the profit thereof is greater than a threshold value.

Abstract translation: 一种用于包括两个群集的处理器的复制传播的方法，每个簇包括第一功能单元和第二功能单元，第一本地寄存器文件和第二本地寄存器文件分别仅由第一和第二功能单元访问， 具有乒乓结构以访问第一和第二本地寄存器文件的全局寄存器文件，所述方法包括以下步骤：（a）列出数据流图的两个节点之间的可能的复制传播路径; （b）根据处理器的约束计算每个复制传播路径的机器周期的利润; 以及（c）如果其利润大于阈值，则通过复制传播路径执行复制传播。

公开(公告)号：US07779412B2

公开(公告)日：2010-08-17

申请号：US11228283

申请日：2005-09-19

Applicant: Yung-Chia Lin ,  Yi-Ping You ,  Chung-Wen Huang ,  Jenq-Kuen Lee

Inventor： Yung-Chia Lin ,  Yi-Ping You ,  Chung-Wen Huang ,  Jenq-Kuen Lee

IPC: G06F9/46 ,  G06F15/00 ,  G06F15/16 ,  G06F13/00 ,  G06F17/50 ,  G06F9/455 ,  G06F1/00

CPC classification number: G06F9/4893 ,  Y02D10/24

Abstract: A system chip includes a plurality of processing elements for performing primary computations of a plurality of tasks, a plurality of non-processing elements for controlling flow of data associated with the tasks among the processing elements, and a main controller including a scheduler, a resource allocation module, and a power management module. The scheduler assigns the tasks on the processing and non-processing elements with reference to time parameters of the processing and non-processing elements. The resource allocation module controls operations of the processing and non-processing elements with reference to task assignments determined by the scheduler. The power management module performs dynamic voltage management upon the processing and non-processing elements according to the scheduled tasks.

Abstract translation: 系统芯片包括用于执行多个任务的主要计算的多个处理元件，用于控制与处理元件之间的任务相关联的数据流的多个非处理元件，以及包括调度器，资源 分配模块和电源管理模块。 调度器根据处理和非处理元素的时间参数分配处理和非处理元素上的任务。 参考由调度器确定的任务分配，资源分配模块控制处理和非处理元件的操作。 电源管理模块根据计划的任务对处理和非处理元件执行动态电压管理。