公开(公告)号：US08510539B2

公开(公告)日：2013-08-13

申请号：US12829711

申请日：2010-07-02

Applicant: Chia Han Lu ,  Chung Ju Wu ,  Jenq Kuen Lee

Inventor： Chia Han Lu ,  Chung Ju Wu ,  Jenq Kuen Lee

IPC: G06F9/44

CPC classification number: G06F9/3012 ,  G06F9/3891

Abstract: A spilling method in register files for a processor is proposed. The processor with Parallel Architecture Core structure includes multiple clusters and a memory. Each cluster includes multiple function units (M-Unit and I-Unit), multiple local register files and a global register file. The local register files are used by the multiple function units, respectively. For a specified live range, the method includes calculating communication costs of the local register files and the global register file in each cluster, and communication cost of the memory for spilling the live range when spilling occurs; calculating use ratios of the local register files and the global register file in each cluster, and use ratio of the memory for the live range; and selecting one of the local register files and the global register file in each cluster and the memory for spilling the live range based on the communication costs and use ratios.

Abstract translation: 提出了处理器寄存器文件的溢出方法。 具有并行架构核心结构的处理器包括多个集群和一个内存。 每个集群包括多个功能单元（M-Unit和I-Unit），多个本地寄存器文件和全局寄存器文件。 本地寄存器文件分别由多个功能单元使用。 对于指定的生存范围，该方法包括计算每个群集中的本地寄存器文件和全局寄存器文件的通信成本，以及溢出发生时溢出生存范围的存储器的通信成本; 计算每个群集中的本地寄存器文件和全局寄存器文件的使用率，并使用存储区的生存区间的比例; 并根据通信成本和使用比例选择每个集群中的一个本地注册文件和全局注册文件，以及用于溢出活动范围的内存。

公开(公告)号：US20130080141A1

公开(公告)日：2013-03-28

申请号：US13614263

申请日：2012-09-13

Applicant: JENQ KUEN LEE ,  PO YU CHEN ,  CHENG YEN LIN

Inventor： JENQ KUEN LEE ,  PO YU CHEN ,  CHENG YEN LIN

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/78

Abstract: The current disclosure discloses a power aware simulation system comprising an embedded multi-core simulation module, a power abstract interpretation module and a C power estimation (CPE) power profiling module. The embedded multi-core simulation module comprises a plurality of digital signal processors (DSP), an external memory and a direct memory access. Each of the plurality of DSPs comprises a DSP core, an instruction cache and a local memory. The power abstract interpretation module is coupled to the plurality of DSPs, the external memory, the DMA and the CPE profiling module, respectively.

Abstract translation: 本公开公开了一种功率感知模拟系统，其包括嵌入式多核仿真模块，功率抽象解释模块和C功率估计（CPE）功率分析模块。 嵌入式多核仿真模块包括多个数字信号处理器（DSP），外部存储器和直接存储器存取。 多个DSP中的每一个包括DSP内核，指令高速缓存和本地存储器。 功率抽象解释模块分别耦合到多个DSP，外部存储器，DMA和CPE分析模块。

公开(公告)号：US20110087922A1

公开(公告)日：2011-04-14

申请号：US12576678

申请日：2009-10-09

Applicant: JENQ KUEN LEE ,  SHOU WEI CHANG

Inventor： JENQ KUEN LEE ,  SHOU WEI CHANG

IPC: G06F11/07

CPC classification number: G06F11/2242

Abstract: A test method for a master-slave concurrent system running on a multicore processor includes the steps of establishing a PFA, otherwise called probabilistic finite automata, or probabilistic finite state machine, for a given regular expression; generating test patterns by running the PFA; splitting and merging the test patterns to generate an interleaved test pattern; and performing test on the master-slave system according to the interleaved test pattern. In an embodiment, the method further includes a step of debugging failures of the multicore processor during testing.

Abstract translation: 用于在多核处理器上运行的主从同时系统的测试方法包括为给定正则表达式建立PFA（否则称为概率有限自动机）或概率有限状态机的步骤; 通过运行PFA生成测试模式; 分割和合并测试图案以产生交错的测试图案; 并根据交错的测试模式对主从系统进行测试。 在一个实施例中，该方法还包括在测试期间调试多核处理器的故障的步骤。

公开(公告)号：US20110083133A1

公开(公告)日：2011-04-07

申请号：US12571986

申请日：2009-10-01

Applicant: JENQ KUEN LEE ,  KUN YUAN HSIEH

Inventor： JENQ KUEN LEE ,  KUN YUAN HSIEH

IPC: G06F9/46 ,  G06F15/16

CPC classification number: G06F9/547 ,  G06F9/544

Abstract: A method of streaming remote procedure invocation for multi-core systems to execute a transmitting thread and an aggregating thread of a multi-core system comprises the steps of: temporarily storing data to be transmitted; activating the aggregating thread if the amount of the temporarily stored data is equal to or greater than a threshold and the aggregating thread is at pause status; pausing the transmitting thread if there is no space to temporarily store the data to be transmitted; retrieving data to be aggregated; activating the transmitting thread if the amount of the data to be aggregated is less than a threshold and the transmitting thread is at pause status; and pausing the aggregating thread if there is no data to be retrieved.

Abstract translation: 一种用于多核系统的远程过程调用的流程执行多核系统的发送线程和聚合线程的方法包括以下步骤：临时存储待发送的数据; 如果临时存储的数据量等于或大于阈值并且聚合线程处于暂停状态，则激活聚合线程; 如果没有空间临时存储要发送的数据，则暂停发送线程; 检索要聚合的数据; 如果要聚合的数据量小于阈值并且发送线程处于暂停状态，则激活发送线程; 并且如果没有要检索的数据，则暂停聚合线程。

公开(公告)号：US20080052694A1

公开(公告)日：2008-02-28

申请号：US11463538

申请日：2006-08-09

Applicant: Jenq Kuen Lee ,  Yung Chia Lin ,  Yi Ping Yu

Inventor： Jenq Kuen Lee ,  Yung Chia Lin ,  Yi Ping Yu

IPC: G06F9/45

CPC classification number: G06F8/441

Abstract: A method of allocating registers for a PAC processor. The PAC processor has a first cluster and a second cluster. Each cluster includes a first functional unit, a second functional unit, a first local register file connected to the first functional unit, a second local register file connected to the second register file, and a global register file having a ping-pong structure formed by a first register bank and a second register bank. After building a Component/Register Type Associated Data Dependency Graph (CRTA-DDG), a functional unit assignment, register file assignment, ping-pong register bank assignment, and cluster assignment of the invention are performed to take full advantage of the properties of a PAC processor.

Abstract translation: 一种为PAC处理器分配寄存器的方法。 PAC处理器具有第一集群和第二集群。 每个集群包括第一功能单元，第二功能单元，连接到第一功能单元的第一本地寄存器文件，连接到第二寄存器堆的第二本地寄存器文件以及具有乒乓结构的全局寄存器堆，所述乒乓结构由 第一个注册银行和第二个注册银行。 在构建组件/寄存器类型相关数据依赖关系图（CRTA-DDG）之后，执行本发明的功能单元分配，寄存器文件分配，乒乓寄存器组分配和集群分配，以充分利用 PAC处理器。

公开(公告)号：US08745599B2

公开(公告)日：2014-06-03

申请号：US13354291

申请日：2012-01-19

Applicant: Jenq Kuen Lee ,  Ming Yu Hung ,  Yuan Shin Hwang ,  Peng Sheng Chen

Inventor： Jenq Kuen Lee ,  Ming Yu Hung ,  Yuan Shin Hwang ,  Peng Sheng Chen

IPC: G06F9/45

CPC classification number: G06F8/434

Abstract: A computer-implemented probabilistic pointer analysis method using SSA form comprises the steps of: evaluating a program in an SSA form comprising a target pointer to determine pointer relations between the target pointer, a plurality of aliased pointers related to the target pointer and at least a probable location of the target pointer; and generating a direct probabilistic relation between the target pointer and the at least a probable location of the target pointer according to the pointer relation.

Abstract translation: 使用SSA形式的计算机实现的概率指针分析方法包括以下步骤：评估包括目标指针的SSA形式的程序，以确定目标指针之间的指针关系，与目标指针相关的多个别名指针和至少一个 目标指针的可能位置; 以及根据所述指针关系，生成所述目标指针与所述目标指针的所述至少可能位置之间的直接概率关系。

公开(公告)号：US20130061022A1

公开(公告)日：2013-03-07

申请号：US13223489

申请日：2011-09-01

Applicant: JENQ KUEN LEE ,  CHI BANG KUAN

Inventor： JENQ KUEN LEE ,  CHI BANG KUAN

IPC: G06F15/76 ,  G06F9/06

CPC classification number: G06F8/441 ,  G06F9/3012 ,  G06F9/3891

Abstract: A method for providing intrinsic supports for a VLIW DSP processor with distributed register files comprises the steps of: generating a program representation with cluster information on instructions of the DSP processor, wherein the cluster information is provided by a program with cluster intrinsic coding; identifying data stream operations indicating parallel instruction sequences applied on different data sets in the program representation; identifying data sharing relations indicating data shared by the data stream operations in the program representation; identifying data aggregation relations indicating results aggregated from the data stream operations in the program representation; and performing register allocation for the DSP processor according to the identified data stream operations, the data sharing relations and the data aggregation relations.

Abstract translation: 一种用于为具有分布式寄存器文件的VLIW DSP处理器提供固有支持的方法包括以下步骤：根据DSP处理器的指令生成具有簇信息的程序表示，其中所述簇信息由具有簇固有编码的程序提供; 识别在程序表示中指示应用于不同数据集合上的并行指令序列的数据流操作; 识别指示由节目表示中的数据流操作共享的数据的数据共享关系; 识别指示从节目表示中的数据流操作聚合的结果的数据聚合关系; 并根据识别的数据流操作，数据共享关系和数据聚合关系为DSP处理器执行寄存器分配。

公开(公告)号：US20100037037A1

公开(公告)日：2010-02-11

申请号：US12490932

申请日：2009-06-24

Applicant: JENQ KUEN LEE ,  LING HUA TSENG ,  CHUNG KAI CHEN

Inventor： JENQ KUEN LEE ,  LING HUA TSENG ,  CHUNG KAI CHEN

IPC: G06F9/40 ,  G06F9/44 ,  G06F9/30

CPC classification number: G06F9/3012 ,  G06F8/441 ,  G06F9/3885 ,  G06F9/3891

Abstract: A method for pipelining instructions on a PAC processor includes determining a minimum initial interval, and grouping the instructions so that the operands of dependent instructions are assigned to the same local register file. The virtual registers of the instructions that have data dependency across the first functional unit and the second functional unit are assigned to a global register file. The instructions are then modulo scheduled based on a current value of initial interval. The virtual registers of the scheduled instructions are allocated to the corresponding register files. If the allocation fails, a set of virtual registers is transferred from the first or second register file to the global register file.

Abstract translation: 用于在PAC处理器上流水线指令的方法包括确定最小初始间隔，并对指令进行分组，使得依赖指令的操作数被分配给相同的本地寄存器文件。 在第一功能单元和第二功能单元之间具有数据依赖性的指令的虚拟寄存器被分配给全局寄存器文件。 然后根据初始间隔的当前值对指令进行模数调度。 调度指令的虚拟寄存器被分配给相应的寄存器文件。 如果分配失败，则一组虚拟寄存器从第一或第二寄存器文件传输到全局寄存器文件。

公开(公告)号：US07650598B2

公开(公告)日：2010-01-19

申请号：US11463538

申请日：2006-08-09

Applicant: Jenq Kuen Lee ,  Yung Chia Lin ,  Yi Ping Yu

Inventor： Jenq Kuen Lee ,  Yung Chia Lin ,  Yi Ping Yu

IPC: G06F12/00

CPC classification number: G06F8/441

Abstract: A method of allocating registers for a PAC processor. The PAC processor has a first cluster and a second cluster. Each cluster includes a first functional unit, a second functional unit, a first local register file connected to the first functional unit, a second local register file connected to the second register file, and a global register file having a ping-pong structure formed by a first register bank and a second register bank. After building a Component/Register Type Associated Data Dependency Graph (CRTA-DDG), a functional unit assignment, register file assignment, ping-pong register bank assignment, and cluster assignment of the invention are performed to take full advantage of the properties of a PAC processor.

Abstract translation: 一种为PAC处理器分配寄存器的方法。 PAC处理器具有第一集群和第二集群。 每个集群包括第一功能单元，第二功能单元，连接到第一功能单元的第一本地寄存器文件，连接到第二寄存器堆的第二本地寄存器文件，以及具有乒乓结构的全局寄存器堆，所述乒乓结构由 第一个注册银行和第二个注册银行。 在构建组件/寄存器类型相关数据依赖关系图（CRTA-DDG）之后，执行本发明的功能单元分配，寄存器文件分配，乒乓寄存器组分配和集群分配，以充分利用 PAC处理器。

公开(公告)号：US20060153125A1

公开(公告)日：2006-07-13

申请号：US11302138

申请日：2005-12-14

Applicant: Jenq-Kuen Lee ,  Jyh-Cheng Chen ,  Cheng-Wei Chen ,  Chung-Kai Chen

Inventor： Jenq-Kuen Lee ,  Jyh-Cheng Chen ,  Cheng-Wei Chen ,  Chung-Kai Chen

IPC: H04Q7/00

CPC classification number: H04W36/0011 ,  H04L67/14 ,  H04W80/04

Abstract: A roaming method for maintaining connectivity between a client and a server through heterogeneous wireless networks includes the steps of establishing an initial connection between the client and the server through a first selected one of the heterogeneous wireless networks, detecting disconnection of the initial connection, and establishing a current connection between the client and server through a second selected one of the heterogeneous wireless networks upon detecting that the initial connection has been disconnected. A system, which includes the client and the server, for realizing the roaming method is also disclosed.

Abstract translation: 用于通过异构无线网络来维护客户端和服务器之间的连接的漫游方法包括以下步骤：通过异构无线网络中的第一选定的一个建立客户端与服务器之间的初始连接，检测初始连接的断开，以及建立 当检测到初始连接已被断开时，通过异构无线网络中的第二选定的一个异常无线网络在客户端和服务器之间的当前连接。 还公开了一种用于实现漫游方法的包括客户端和服务器的系统。