公开(公告)号：US5706443A

公开(公告)日：1998-01-06

申请号：US241904

申请日：1994-05-11

Applicant: James T. Brady ,  Damon W. Finney ,  Michael H. Hartung ,  Donald J. Lang ,  Jaishankar M. Menon ,  David R. Nowlen ,  Calvin K. Tang

Inventor： James T. Brady ,  Damon W. Finney ,  Michael H. Hartung ,  Donald J. Lang ,  Jaishankar M. Menon ,  David R. Nowlen ,  Calvin K. Tang

IPC: G06F13/12 ,  G06F5/06 ,  G06F13/38 ,  G06F13/00

CPC classification number: G06F5/06

Abstract: A system that enables pipelining of data to and from a memory includes multiple control block data structures which indicate amounts of data stored in the memory. An input port device receives and stores in memory, data segments of a received data message and only updates status information in the software control blocks when determined quantities of the data segments are stored. An output port is responsive to a request for transmission of a portion of the received data and to a signal from the input port that at least a first control count of data segments of the received data are present in memory. The output port then outputs the stored data segments from memory but discontinues the action if, before the required portion of the received data is outputted, software control blocks indicate that no further stored data segments are available for outputting. The input port then updates the software control blocks when newly arrived and stored data segments reach a second control count value, the updating occurring irrespective of whether the determined quantity of the received data has been stored in memory.

Abstract translation: 使得数据能够流向存储器和从存储器流出的系统包括指示存储在存储器中的数据量的多个控制块数据结构。 输入端口设备在存储器中接收并存储接收的数据消息的数据段，并且仅在存储确定的数据段的数量时才更新软件控制块中的状态信息。 输出端口响应于对接收到的数据的一部分的传输的请求和来自输入端口的信号，接收到的数据的数据段的至少第一控制计数存在于存储器中。 然后，输出端口从存储器输出存储的数据段，但是如果在输出所接收的数据的所需部分之前，软件控制块指示没有进一步存储的数据段可用于输出，则停止该动作。 然后，当新到达时，输入端口更新软件控制块，并且存储的数据段达到第二控制计数值，无论所确定的接收数据量是否已被存储在存储器中，更新发生。

公开(公告)号：US5488701A

公开(公告)日：1996-01-30

申请号：US340977

申请日：1994-11-17

Applicant: James T. Brady ,  Jaishankar M. Menon

Inventor： James T. Brady ,  Jaishankar M. Menon

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  G11C29/00 ,  G06F11/34

CPC classification number: G11C29/74 ,  G06F11/1088 ,  G06F12/023 ,  G06F2003/0697 ,  G06F3/0601

Abstract: In a log structured array (LSA) storage subsystem, a method for recovering from a storage device failure which incorporates the LSA write and garbage collection procedures, thereby simplifying the recovery process and eliminating the need for dedicated or distributed sparing schemes. Data is distributed across the array in N+P parity groups. Upon a device failure, each lost data block is reconstructed from the remaining blocks of its parity group. The reconstructed block is then placed in the subsystem write buffer to be processed with incoming write data, and new parity is generated for the remaining N-1 data blocks of the group. A lost parity block is replaced by first moving one of the data blocks of its parity group to the write buffer, and then generating new parity for the remaining N-1 data blocks. Also disclosed is a storage subsystem implementing the preceding recovery method.

Abstract translation: 在日志结构化阵列（LSA）存储子系统中，一种从存储设备故障中恢复的方法，其中包含了LSA写入和垃圾收集过程，从而简化了恢复过程，并且消除了对专用或分布式备份方案的需求。 数据在N + P个奇偶校验组中分布在阵列中。 在设备故障时，从其奇偶校验组的剩余块重构每个丢失的数据块。 然后将重建的块放置在子系统写入缓冲器中，以进入写入数据进行处理，并为该组的剩余N-1个数据块生成新的奇偶校验。 丢失的奇偶校验块被首先将其奇偶校验组的数据块中的一个移动到写缓冲器，然后为剩余的N-1个数据块生成新的奇偶校验。 还公开了实现上述恢复方法的存储子系统。

公开(公告)号：US5418921A

公开(公告)日：1995-05-23

申请号：US878810

申请日：1992-05-05

Applicant: James E. Cortney ,  Jaishankar M. Menon

Inventor： James E. Cortney ,  Jaishankar M. Menon

IPC: G06F3/06 ,  G06F11/10 ,  G06F11/20 ,  G06F12/08 ,  G06F12/16 ,  G06F13/00 ,  G06F12/00

CPC classification number: G06F11/1666 ,  G06F11/1008 ,  G06F11/1076 ,  G06F12/0804 ,  G06F11/20 ,  G06F12/0866

Abstract: A method and means using a fast write in order to eliminate DASD time from the write response time as seen by the host; eliminate some DASD writes due to overwrites caused by later host writes to previously updated blocks in cache; and reduce DASD seeks because destages will be postponed until many destages can be done to a track or cylinder. This is effectuated by destaging from the cache only the least recently referenced original or updated block and all other original or updated blocks occupying the same logical track and ordered in a predefined lower LRU range, the destage being initiated responsive to a cache miss. The destaging step is selectable from a set of destaging steps varying in their robustness.

Abstract translation: 一种使用快速写入的方法和手段，以消除主机看到的写入响应时间的DASD时间; 消除一些DASD写入，这是由于以后主机写入高速缓存中先前更新的块所导致的覆盖; 并减少DASD寻求，因为将会推迟到达一个轨道或圆柱体，直到有许多到达目的地。 这是通过从高速缓存仅通过最不近期参考的原始或更新块以及占据相同逻辑磁道并且在预定义的较低LRU范围内排序的所有其它原始或更新块来降级，该恢复是响应于高速缓存未命中发起的。 降级步骤可以从其鲁棒性变化的一组降级步骤中选择。

公开(公告)号：US5375128A

公开(公告)日：1994-12-20

申请号：US600034

申请日：1990-10-18

Applicant: Jaishankar M. Menon ,  James M. Kasson

Inventor： Jaishankar M. Menon ,  James M. Kasson

IPC: G06F3/06 ,  G06F11/10 ,  G11B20/18 ,  H03M13/00

CPC classification number: G06F11/1076 ,  G06F11/1008 ,  G06F3/0601 ,  G11B20/1833 ,  G06F2003/0692

Abstract: A method for update writing in an array of DASDs in a reduced number of DASD track cycles. The method involves distributing data and parity blocks for each parity group across the array in failure independent form and reserving unused space. During a first cycle, the old data and parity blocks are read. The new parity is calculated and shadow written into reserved unused space located before the old parity block recurs. The amended data is either written in place during a second cycle or shadow written into reserved space during a subsequent portion of the first cycle.

Abstract translation: 一种用于在DASD轨道周期数量减少的DASD阵列中更新写入的方法。 该方法包括以故障独立形式在阵列上为每个奇偶校验组分配数据和奇偶校验块，并保留未使用的空间。 在第一周期期间，读取旧的数据和奇偶校验块。 计算新奇偶校验并将影子写入位于旧奇偶校验块之前的未预留空闲区域。 在第一周期的后续部分期间，将经修改的数据写入到第二周期中的位置或写入保留空间的阴影。

公开(公告)号：US5258984A

公开(公告)日：1993-11-02

申请号：US714969

申请日：1991-06-13

Applicant: Jaishankar M. Menon ,  Richard L. Mattson ,  Spencer W. Ng

Inventor： Jaishankar M. Menon ,  Richard L. Mattson ,  Spencer W. Ng

IPC: G06F12/16 ,  G06F3/06 ,  G06F11/10 ,  G06F11/20 ,  G11C29/00

CPC classification number: G06F11/2094 ,  G06F11/1076 ,  G06F11/1662 ,  G11C29/88 ,  G06F2211/1028

Abstract: A method and means in which data and parity blocks forming parity groups together with spare blocks are distributed over array block locations according to at least one combinatorial design, each group having N data and P parity blocks. The combinatorial designs yield uniform or balanced loading thereby minimizing the number of accesses to reconstruct missing data and parity blocks and their copyback into spare block locations, and, minimize the number of accesses to the reconstructed data referenced subsequent to its copyback. Distributions of the spare block capacity of one or two DASDs are shown over single and multiple arrays and shared among multiple arrays. Parity block distribution although ancillary to spare distribution enhances throughput and reduces the number of accesses for rebuild etc.

公开(公告)号：US5257362A

公开(公告)日：1993-10-26

申请号：US666289

申请日：1991-03-08

Applicant: Jaishankar M. Menon

Inventor： Jaishankar M. Menon

IPC: G06F3/06 ,  G06F11/10 ,  G11B20/18

CPC classification number: G06F11/1076 ,  G06F11/1008 ,  G06F3/0601 ,  G11B20/1833 ,  G06F2003/0692

Abstract: Write update of variable length records stored in row major order on an array of N DASDs is facilitated by utilizing the correlation between byte offsets of a variable length record and the byte offset of a byte level parity image of data stored on the same track across N-1 other DASDs.

公开(公告)号：US5542066A

公开(公告)日：1996-07-30

申请号：US172527

申请日：1993-12-23

Applicant: Richard L. Mattson ,  Jaishankar M. Menon

Inventor： Richard L. Mattson ,  Jaishankar M. Menon

IPC: G06F11/10 ,  G06F11/34 ,  G06F12/08 ,  G11C29/00 ,  G06F12/00

CPC classification number: G06F12/0804 ,  G06F11/1008 ,  G06F11/3409 ,  G06F11/3485 ,  G06F12/0866 ,  G11C29/74

Abstract: A controller for a disk array with parity and sparing includes a non-volatile cache memory and optimizes the destaging process for blocks from the cache memory to both maximize the cache hit ratio and minimize disk utilization. The invention provides a method for organizing the disk array into segments and dividing the cache memory into groups in order of least recently used memory locations and then determining metrics that permit the disk array controller to identify the cache memory locations having the most dirty blocks by segment and group and to identify the utilization rates of the disks. These characteristics are considered to determine when, what, and how to destage. For example, in terms of maximizing the cache hit ratio, when the percentage of dirty blocks in a particular group of the cache memory locations reaches a predetermined level, destaging is begun. The destaging operation continues until the percentage of dirty blocks decreases to a predetermined level. In terms of minimizing disk utilization, all of the dirty blocks in a segment having the most dirty blocks in a group are destaged.

Abstract translation: 用于具有奇偶校验和备用的磁盘阵列的控制器包括非易失性高速缓存存储器，并且优化来自高速缓冲存储器的块的降级处理以最大化高速缓存命中率并最小化磁盘利用率。 本发明提供了一种用于将磁盘阵列组织成段并将高速缓存存储器按照最近最少使用的存储器位置的顺序划分成组的方法，然后确定允许磁盘阵列控制器通过片段识别具有最脏块的高速缓冲存储器位置的度量 并分组并确定磁盘的使用率。 这些特征被认为是决定什么时候，什么以及如何去世的。 例如，就最大化高速缓存命中率而言，当高速缓冲存储器位置的特定组中的脏块的百分比达到预定水平时，开始着陆。 破坏操作继续，直到脏块的百分比减小到预定水平。 在最小化磁盘利用率的情况下，具有组中最脏的块的段中的所有脏块都将被排除。

公开(公告)号：US5459853A

公开(公告)日：1995-10-17

申请号：US979740

申请日：1992-11-23

Applicant: John S. Best ,  Steven R. Hetzler ,  Roger F. Hoyt ,  Jaishankar M. Menon ,  Michael F. Mitoma

Inventor： John S. Best ,  Steven R. Hetzler ,  Roger F. Hoyt ,  Jaishankar M. Menon ,  Michael F. Mitoma

IPC: G06F3/06 ,  G06F11/10 ,  G11B20/10 ,  G11B20/12 ,  G06F12/00 ,  G06F12/04

CPC classification number: G06F11/1076 ,  G06F11/1008 ,  G06F3/0601 ,  G06F2003/0697 ,  G11B20/1258

Abstract: A method for operating a synchronized array of fixed block (FBA) formatted Direct Access Storage Devices (DASDs) to store and update variable-length (CKD) formatted records. This method is suitable for use with DASDs that obtain high recording density by using read and write head technology requiring "micro-jogging" to adjust for differing read and write head alignment or banded disk architecture having a higher block count in the outer tracks than in the inner tracks. Magneto-resistive heads may require micro-jogging to realign the write head for recording after reading the physical track location. The invention employs a DASD staggered array architecture having logical tracks consisting of diagonal-major sequences of consecutive blocks arranged in a predetermined wrap-around manner such as a topological cylinder or torus. The minimum necessary number of DASDs (N) in the staggered array is limited by the fixed block size (B), the interblock gap size (G), the average DASD data transfer rate (D), and the micro-jog delay time (T). A (N+1).sup.th DASD may be added to record the parity of each diagonal-major sequence for improved fault-tolerance.

Abstract translation: 一种用于操作固定块（FBA）格式化的直接存取存储设备（DASD）的同步阵列以存储和更新可变长度（CKD）格式记录的方法。 该方法适用于通过使用需要“微点动”的读写头技术来获得高记录密度的DASD，用于调整不同的读写头对准或带外磁盘结构，在外轨道中具有较高的块数，而不是 内轨。 在读取物理轨道位置之后，磁阻头可能需要微型点动来重新对准写入头进行记录。 本发明采用具有逻辑轨迹的DASD交错阵列架构，其逻辑轨道由以诸如拓扑柱面或环面的预定绕环方式布置的连续块的对角线主序列组成。 交错阵列中DASD（N）的最小必需数量受固定块大小（B），块间间隙大小（G），平均DASD数据传输速率（D）和微点动延迟时间（D） T）。 可以添加A（N + 1）DASD来记录每个对角线主序列的奇偶校验，以提高容错能力。

公开(公告)号：US5301297A

公开(公告)日：1994-04-05

申请号：US725696

申请日：1991-07-03

Applicant: Jaishankar M. Menon ,  Leighton C. Wood, Jr.

Inventor： Jaishankar M. Menon ,  Leighton C. Wood, Jr.

IPC: G06F3/06 ,  G06F11/10 ,  G06F11/20 ,  G06F12/16 ,  G06F12/06

CPC classification number: G06F11/1076 ,  G06F2211/1045

Abstract: A method and apparatus teaching insertion of addressing indirection to form and to access an array hierarchy expressly permitting the concurrency of a high level RAID array, the bandwidth and degraded mode operation sustainable by a lower level RAID array, and after a DASD failure minimum spanning involvement when the array is rebuilding and rewriting missing data to a spare logical device. Also, disclosed are the accessing of variable length records on the array hierarchy; array hierarchy in which RAID 5 arrays have dissimilar number of logic devices (lower level RAID arrays) and interleave depths; formation of logical arrays using fractional storage defined onto real DASD subsets; and the defining of logical devices onto DASDs distributed in the same or different physical clusters of DASDs and the rebuild operation thereof.

Abstract translation: 一种教导插入寻址间接以形成和访问阵列层次结构的方法和装置，明确允许高级RAID阵列的并发，由较低级RAID阵列可持续的带宽和降级模式操作，以及在DASD故障最小跨越涉及之后 当阵列正在重建并将缺失的数据重写到备用逻辑设备时。 另外，公开了访问数组层级上的可变长度记录; 阵列层次结构，其中RAID 5阵列具有不同数量的逻辑器件（较低级RAID阵列）和交错深度; 使用定义在实际DASD子集上的分数存储来形成逻辑阵列; 以及在分布在相同或不同的DASD物理簇中的DASD上的逻辑设备的定义及其重建操作。

公开(公告)号：US5271012A

公开(公告)日：1993-12-14

申请号：US653596

申请日：1991-02-11

Applicant: Miguel M. Blaum ,  Hsieh T. Hao ,  Richard L. Mattson ,  Jaishankar M. Menon

Inventor： Miguel M. Blaum ,  Hsieh T. Hao ,  Richard L. Mattson ,  Jaishankar M. Menon

IPC: G06F3/06 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F12/16 ,  G11B20/18 ,  G11C29/00 ,  H03M13/11

CPC classification number: G11C29/88 ,  G06F11/1092 ,  G11B20/1833 ,  H03M13/11 ,  G06F11/1012

Abstract: A method and means for encoding data written onto an array of M synchronous DASDs and for rebuilding onto spare DASD array capacity when up to two array DASD fail. Data is mapped into the DASD array using an (M-1)*M data array as the storage model where M is a prime number. Pairs of simple parities are recursively encoded over data in respective diagonal major and intersecting row major order array directions. The encoding traverse covering a topologically cylindrical path. Rebuilding data upon unavailability of no more than two DASDs merely requires accessing the data array and repeating the encoding step where the diagonals are oppositely sloped and writing the rebuilt array back to onto M DASDs inclusive of the spare capacity.