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1.发明授权Mechanism for implementing one machine cycle executable trap instructions in a primitive instruction set computing system 失效在原语指令集计算系统中实现一个机器循环可执行陷阱指令的机制
公开(公告)号：US4589065A
公开(公告)日：1986-05-13
申请号：US509733
申请日：1983-06-30
CPC分类号： G06F9/4812 , G06F9/30021
摘要： A mechanism for performing a run-time storage address validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its function in one machine cycle in the event that a trap exception does not cause an interrupt. In the rare instance when an interrupt is necessary, a number of machine cycles will be impacted. The mechanism comprises a minimum amount of logic circuitry for determining the trap condition operating in conjunction with conventional, previously existing compare, branch instruction testing, and interrupt generation circuitry.
摘要翻译： 一种用于在一个机器周期内执行运行时存储地址有效性检查的机制。 该机制与智能编译器一起运行，无需硬件实现存储有效性检查。 更具体地说，在陷阱异常不引起中断的情况下，该机制在一个机器周期中执行其功能。 在少数情况下，当需要中断时，会影响多个机器周期。 该机构包括用于确定与传统的先前存在的比较分支指令测试和中断产生电路一起操作的陷阱条件的最小量的逻辑电路。
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公开(公告)号：US4588966A
公开(公告)日：1986-05-13
申请号：US679971
申请日：1984-12-10
CPC分类号： H03B9/141
摘要： A millimeter wavelength oscillator combining a mechanically tunable resonating cavity oscillator element with an electronically tunable solid state diode element provides a basic stable steady wave energy source with fine-tuning capabilities not possible with a resonating cavity oscillator alone, and with an apparatus structure which is light in weight, compact, mechanically sturdy, and with easily accessible and quickly replaceable component parts.
摘要翻译： 组合机械可调谐谐振腔元件和电子可调谐固体二极管元件的毫米波长振荡器提供了一个基本稳定的稳定波能量源，其具有单独谐振空腔振荡器不可能实现的微调功能，并且具有轻便的装置结构 重量轻，紧凑，机械坚固，易于接近和快速更换的部件。
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3.发明授权Method and means for encoding and rebuilding data contents of up to two unavailable DASDs in an array of DASDs 失效用于在DASD阵列中编码和重建多达两个不可用DASD的数据内容的方法和手段
公开(公告)号：US5271012A
公开(公告)日：1993-12-14
申请号：US653596
申请日：1991-02-11
IPC分类号： G06F3/06 , G06F11/10 , G06F11/16 , G06F11/20 , G06F12/16 , G11B20/18 , G11C29/00 , H03M13/11
CPC分类号： G11C29/88 , G06F11/1092 , G11B20/1833 , H03M13/11 , G06F11/1012
摘要： A method and means for encoding data written onto an array of M synchronous DASDs and for rebuilding onto spare DASD array capacity when up to two array DASD fail. Data is mapped into the DASD array using an (M-1)*M data array as the storage model where M is a prime number. Pairs of simple parities are recursively encoded over data in respective diagonal major and intersecting row major order array directions. The encoding traverse covering a topologically cylindrical path. Rebuilding data upon unavailability of no more than two DASDs merely requires accessing the data array and repeating the encoding step where the diagonals are oppositely sloped and writing the rebuilt array back to onto M DASDs inclusive of the spare capacity.
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4.发明授权(k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions 失效（k） - 用于并行执行固有顺序指令的一次性流水线处理器
公开(公告)号：US4594655A
公开(公告)日：1986-06-10
申请号：US475286
申请日：1983-03-14
申请人： Hsieh T. Hao , Huei Ling , Howard E. Sachar , Jeffrey Weiss , Yannis J. Yamour
发明人： Hsieh T. Hao , Huei Ling , Howard E. Sachar , Jeffrey Weiss , Yannis J. Yamour
CPC分类号： G06F9/3889 , G06F9/3853
摘要： Equipping a secondary data flow facility with additional capability, to emulate for certain operations the simultaneous processing of the prerequisite instruction and the dependent instruction, significantly improves simultaneous pipeline processing of inherently sequential instructions (k)-at-a-time, by eliminating delays for calculating prerequisite operands. For example, Instruction A+B=Z1 followed by Instruction Z1+C=Z2 is inherently sequential, with A+B=Z1 the prerequisite instruction and Z1+C=Z2 the dependent instruction. The specially equipped secondary data flow facility does not wait for Z1, the apparent input operand from the prerequisite instruction; it simulates Z1 instead, performing A+B+C=Z2 in parallel with A+B=Z1. All data flow facilities need not be fully equipped for all instructions; the secondary data flow facility may be generally less massive than a primary data flow facility, but is more sophisticated in a critical organ, such as the adder. The three-input adder of the secondary data flow facility emulates the result of a two-input adder of a primary data flow facility, occuring simultaneously in the two-input primary data flow facility adder, adding the third operand to the emulated result, without delay. The instruction unit decodes the instruction sequence normally to control (k)-at-a-time execution where there are no instruction interlocks or dependencies; to delay execution of dependent instructions until operands become available; and to reinstate (k)-at-a-time execution in a limited number of cases by using the additional capability of the secondary data flow facility to emulate the prerequisite operands. A control unit performs housekeeping to execute the instructions.
摘要翻译： 为具有附加功能的二次数据流设施提供模拟，以便为某些操作模拟先决条件指令和相关指令的同时处理，通过消除延迟时间来显着提高固有顺序指令（k）的同时流水线处理 计算先决条件操作数。 例如，指令A + B = Z1后跟指令Z1 + C = Z2是固有顺序的，A + B = Z1是先决条件指令，Z1 + C = Z2是相关指令。 专门设备的二次数据流设备不等待来自前提指令的表观输入操作数Z1， 它模拟Z1，而与A + B = Z1并行执行A + B + C = Z2。 所有数据流设施不需要为所有指令设备齐全; 辅助数据流设施通常可能不如初级数据流设施那么庞大，但在诸如加法器的关键器官中更复杂。 二次数据流设施的三输入加法器模拟主数据流设施的双输入加法器的结果，同时发生在双输入主数据流设备加法器中，将第三操作数与仿真结果相加，而没有 延迟。 指令单元正常地解码指令序列以控制（k）一次执行，其中没有指令互锁或依赖; 延迟依赖指令的执行，直到操作数变得可用; 并且通过使用辅助数据流设施的附加能力来模拟先决操作数，在有限数量的情况下恢复（k）一次执行。 控制单元执行内务处理以执行指令。
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5.发明授权Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system 失效实现一个机器循环可执行掩码并在原语指令集计算系统中旋转指令的机制
公开(公告)号：US4569016A
公开(公告)日：1986-02-04
申请号：US509836
申请日：1983-06-30
申请人： Hsieh T. Hao , Peter W. Markstein , George Radin
发明人： Hsieh T. Hao , Peter W. Markstein , George Radin
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30167
摘要： A mechanism for performing fast and efficient full shift, merge, insert and bit alignment functions within one operating machine cycle of a host primitive instructions set computing system. In general, the circuitry performs a ring shift under control of a mask. The circuitry further combines essentially parallel rotate and mask and merge functions all executable in one machine cycle. The circuitry further allows the provision of powerful bit, digit, and bit rotate with mask instructions which are particularly useful primitive operations for decimal packing and unpacking functions as well as for implementing floating point preshifting and normalization functions.
摘要翻译： 一种用于在主机原语指令集计算系统的一个操作机器周期内执行快速且有效的全移位，合并，插入和位对齐功能的机制。 通常，电路在掩模的控制下执行环移。 该电路进一步组合了在一个机器周期中所有可执行的基本上并行的旋转和掩模和合并功能。 电路还允许使用掩码指令提供强大的位，位和位旋转，这些指令对于十进制打包和解包功能以及实现浮点预移动和归一化功能都是特别有用的原始操作。
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公开(公告)号：US5412661A
公开(公告)日：1995-05-02
申请号：US957293
申请日：1992-10-06
申请人： Hsieh T. Hao , Spencer W. Ng
发明人： Hsieh T. Hao , Spencer W. Ng
CPC分类号： G06F11/201 , G06F11/1008 , G06F11/1076 , G11B20/1833
摘要： A data storage system architecture having an array of small data storage disks, organized into logical rows and columns, with each disk coupled to two disk controllers via two independent controller-disk interconnects. No two disks are coupled to the same pair of controllers. In this data storage system architecture, the component disks are arranged in parity groups of variable size. Within each parity group, failure of one disk sector can be recovered through data reconstruction using data from other disks in the parity group. One or more disks can be reserved as hot standbys for substitution on failure, automatically replacing any failing disk.
摘要翻译： 数据存储系统架构具有组织成逻辑行和列的小型数据存储磁盘阵列，每个磁盘通过两个独立的控制器 - 磁盘互连耦合到两个磁盘控制器。 没有两个磁盘耦合到同一对控制器。 在这种数据存储系统架构中，组件磁盘以可变大小的奇偶校验组排列。 在每个奇偶校验组内，可以通过使用奇偶校验组中其他磁盘的数据进行数据重建来恢复一个磁盘扇区的故障。 可以将一个或多个磁盘保留为热备份，以便在故障时进行替换，自动替换任何故障磁盘。
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7.发明授权Error correction capability varied with track location on a magnetic or optical disk 失效在磁性或光盘上跟踪位置变化的错误校正能力
公开(公告)号：US5068858A
公开(公告)日：1991-11-26
申请号：US455197
申请日：1989-12-21
申请人： Miguel M. Blaum , Hsieh T. Hao
发明人： Miguel M. Blaum , Hsieh T. Hao
CPC分类号： H03M13/35 , G11B20/1833 , G11B20/1258
摘要： A method for implementing error-correcting codes for disks, wherein the statistics of error vary according to the radius of the location being accessed.A Reed-Solomon code is selected having data bytes and redundant bytes and an error-correcting capability sufficient to protect against an anticipated worst case or errors.The number of redundant bytes in that code, and thereby the number of correctable errors, is progressively reduced in respective concentric areas of the disk according to the statistics of error for such areas, for thereby progressively reducing the number of correctable errors as the need for error correction capability decreases.For multiband recording, the areas are concentric bands in each of which data is recorded at a clock frequency substantially proportional to its inner diameter; and in such case, the number of redundant bytes is reduced progressively in each successive band toward the innermost band.For conventional recording, the areas are concentric tracks recorded at substantially the same frequency; and in such case, the number of redundant bytes is reduced toward the outermost concentric area.This method may also be used to increase correction capability periodically when capability decreases, due for example to corrosion of a write-once optical disk.
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公开(公告)号：US4589087A
公开(公告)日：1986-05-13
申请号：US509744
申请日：1983-06-30
CPC分类号： G06F9/30014 , G06F9/30094
摘要： A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency. Still more particularly, the condition register architecture provides for the efficient handling of multiply and divide operations and provides for the more efficient execution of certain decimal operations within such a reduced instruction set host computer system.
摘要翻译： 一种包括用于简化指令集计算系统中的扩展条件寄存器的机制，其有助于在系统上执行单个机器周期指令，并进一步提供有效执行不易于在单个机器中完成的更复杂的指令 周期。 更具体地，提供了用于设置扩展条件寄存器的位的机制，由此在机器中断之后可以进行更有效的重新启动，并且由此某些多步逻辑和算术运算的中间操作的结果被保持在条件寄存器中，以便 这种多步操作的循环时间可以保持最小，并且在必要时可以以更高的效率执行。 更具体地，条件寄存器架构提供对乘法和除法运算的有效处理，并且提供在这种简化的指令集主计算机系统内更有效地执行某些十进制运算。
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