公开(公告)号：US5577236A

公开(公告)日：1996-11-19

申请号：US367514

申请日：1994-12-30

Applicant: Mark C. Johnson ,  Donald J. Lang ,  Sudha Sarma ,  Forrest L. Wade ,  Adalberto G. Yanes

Inventor： Mark C. Johnson ,  Donald J. Lang ,  Sudha Sarma ,  Forrest L. Wade ,  Adalberto G. Yanes

IPC: G06F13/16 ,  G11C7/10 ,  G06F12/00

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/1072

Abstract: A memory controller reads data from a memory bank of synchronous RAM during a small and variable data valid window, by compensating for delays in receiving the data caused by memory loading, chip and card manufacturing process variations, and the like. The memory controller includes a system clock driver to supply the memory bank with a clock reference signal. A sampling clock provides an assortment of sampling clock signals duplicative of the system clock signal, with various delays. A command driver initiates Read operations in the memory bank by relaying Read command signals to the memory bank. In response to the level of memory loading, such as the number of memory modules present in the memory bank, a clock selector directs a selected one of the sampling clock signals to a delay module, which replicates any delay the system clock driver may have. If desired, an additional, user-selectable supplementary delay unit may be used to increase the delay provided by the delay module, thereby increasing or offsetting the delay of the selected sampling clock signal. The delay module provides a delayed clock signal to synchronize receipt of Read data signals from the memory bank at a clocked latch, enabling the latch to receive the Read data signals during the appropriate data valid window. Specifically, the latch is activated by receipt of Read command signals, which may be coordinated, for example, with the rising edge of the delayed clock signal. The latched Read data signals are then available for use by other logic circuitry.

Abstract translation: 存储器控制器通过补偿由存储器加载，芯片和卡制造过程变化等导致的数据的延迟，从而在小且可变的数据有效窗口期间从同步RAM的存储体读取数据。 存储器控制器包括用于向存储体提供时钟参考信号的系统时钟驱动器。 采样时钟提供与系统时钟信号重复的各种采样时钟信号，具有各种延迟。 命令驱动程序通过将Read命令信号中继到存储体来启动存储体中的Read操作。 响应于诸如存储器组中存在的存储器模块的数量的存储器加载的级别，时钟选择器将选择的一个采样时钟信号引导到延迟模块，延迟模块复制系统时钟驱动器可能具有的任何延迟。 如果需要，可以使用附加的用户可选择的辅助延迟单元来增加由延迟模块提供的延迟，从而增加或抵消所选择的采样时钟信号的延迟。 延迟模块提供延迟的时钟信号，以在时钟锁存器上同步来自存储体的读取数据信号的接收，使得锁存器能够在适当的数据有效窗口期间接收读取数据信号。 具体地，锁存器通过接收可以例如与延迟的时钟信号的上升沿协调的读命令信号来激活。 锁存的读数据信号可供其他逻辑电路使用。

公开(公告)号：US4969120A

公开(公告)日：1990-11-06

申请号：US310406

申请日：1989-02-13

Applicant: Michael J. Azevedo ,  Paul W. Hunter ,  Donald J. Lang

Inventor： Michael J. Azevedo ,  Paul W. Hunter ,  Donald J. Lang

IPC: G06F13/362 ,  G06F13/14 ,  G06F13/364

CPC classification number: G06F13/14 ,  G06F13/364

Abstract: An access control or arbitrator for a shared resource, such as a time-slotted bus, groups requests according to priorities of the requests. The time slots are grouped into sets, each set having a number of successive time slots equal to the number of sources supplying access requests having a highest priority. In a highest priority group, each source supplying a highest priority access request is guaranteed access in respective ones of said time slots in each set of time slots. When any time slot is not being used by a high priority request, low priority requests then have access to the unused time slot. Lower priority groups of access requests are handled in accordance with a different algorithm, such as a round robin priority algorithm.

公开(公告)号：US5706443A

公开(公告)日：1998-01-06

申请号：US241904

申请日：1994-05-11

Applicant: James T. Brady ,  Damon W. Finney ,  Michael H. Hartung ,  Donald J. Lang ,  Jaishankar M. Menon ,  David R. Nowlen ,  Calvin K. Tang

Inventor： James T. Brady ,  Damon W. Finney ,  Michael H. Hartung ,  Donald J. Lang ,  Jaishankar M. Menon ,  David R. Nowlen ,  Calvin K. Tang

IPC: G06F13/12 ,  G06F5/06 ,  G06F13/38 ,  G06F13/00

CPC classification number: G06F5/06

Abstract: A system that enables pipelining of data to and from a memory includes multiple control block data structures which indicate amounts of data stored in the memory. An input port device receives and stores in memory, data segments of a received data message and only updates status information in the software control blocks when determined quantities of the data segments are stored. An output port is responsive to a request for transmission of a portion of the received data and to a signal from the input port that at least a first control count of data segments of the received data are present in memory. The output port then outputs the stored data segments from memory but discontinues the action if, before the required portion of the received data is outputted, software control blocks indicate that no further stored data segments are available for outputting. The input port then updates the software control blocks when newly arrived and stored data segments reach a second control count value, the updating occurring irrespective of whether the determined quantity of the received data has been stored in memory.

Abstract translation: 使得数据能够流向存储器和从存储器流出的系统包括指示存储在存储器中的数据量的多个控制块数据结构。 输入端口设备在存储器中接收并存储接收的数据消息的数据段，并且仅在存储确定的数据段的数量时才更新软件控制块中的状态信息。 输出端口响应于对接收到的数据的一部分的传输的请求和来自输入端口的信号，接收到的数据的数据段的至少第一控制计数存在于存储器中。 然后，输出端口从存储器输出存储的数据段，但是如果在输出所接收的数据的所需部分之前，软件控制块指示没有进一步存储的数据段可用于输出，则停止该动作。 然后，当新到达时，输入端口更新软件控制块，并且存储的数据段达到第二控制计数值，无论所确定的接收数据量是否已被存储在存储器中，更新发生。

公开(公告)号：US5675736A

公开(公告)日：1997-10-07

申请号：US685770

申请日：1996-07-24

Applicant: James Thomas Brady ,  Damon W. Finney ,  Michael Howard Hartung ,  Paul Wayne Hunter ,  Michael Anthony Ko ,  Donald J. Lang ,  Noah R. Mendelsohn ,  Jaishankar Moothedath Menon ,  David Ronald Nowlen

Inventor： James Thomas Brady ,  Damon W. Finney ,  Michael Howard Hartung ,  Paul Wayne Hunter ,  Michael Anthony Ko ,  Donald J. Lang ,  Noah R. Mendelsohn ,  Jaishankar Moothedath Menon ,  David Ronald Nowlen

IPC: G06F13/14 ,  G06F13/00 ,  G06F15/16 ,  G06F15/177 ,  H04L12/56 ,  H04L29/04 ,  H04L29/06

CPC classification number: H04L29/06 ,  H04L45/22 ,  H04L45/28 ,  H04L69/14

Abstract: A distributed data processing system includes a plurality of nodes interconnected by bidirectional communication links. Each node includes a control message line for handling of control messages and a control memory for storing the control messages. Each node further includes data message line for handling of data messages and a data memory for storing the data messages. A processor in the node causes the data message line to queue and dispatch data messages from the data memory and the control message line to queue and dispatch control messages from the control memory. Each node includes N bidirectional communication links enabling the node to have at least twice as much input/output bandwidth as the control message line and data message line, combined. An input/output switch includes a routing processor and is coupled between the N bidirectional communication links, the data message line and control message line. The input/output switch dispatches either a control message or a data message over at least one of the bidirectional communication links in accordance with an output from the routing control processor, thereby enabling each communication link to carry either data or control messages. If a communication link is busy with either a control or a data message, the routing control processor increments to another communication link to enable dispatch of a queued message.

Abstract translation: 分布式数据处理系统包括通过双向通信链路互连的多个节点。 每个节点包括用于处理控制消息的控制消息线和用于存储控制消息的控制存储器。 每个节点还包括用于处理数据消息的数据消息行和用于存储数据消息的数据存储器。 节点中的处理器使得数据消息行从数据存储器和控制消息行排队和调度数据消息，以从控制存储器排队和调度控制消息。 每个节点包括N个双向通信链路，使得该节点具有至少两倍于控制消息行和数据消息行的输入/输出带宽。 输入/输出开关包括路由处理器，并且耦合在N个双向通信链路，数据消息线路和控制消息线路之间。 输入/输出交换机根据来自路由控制处理器的输出，通过至少一个双向通信链路分派控制消息或数据消息，从而使得每个通信链路能够携带数据或控制消息。 如果通信链路忙于控制或数据消息，则路由控制处理器递增到另一个通信链路以启用排队消息的分派。

公开(公告)号：US5857213A

公开(公告)日：1999-01-05

申请号：US761639

申请日：1996-12-06

Applicant: Michael T. Benhase ,  James Thomas Brady ,  Damon W. Finney ,  Michael Howard Hartung ,  Michael Anthony Ko ,  Donald J. Lang ,  Jaishankar Moothedath Menon

Inventor： Michael T. Benhase ,  James Thomas Brady ,  Damon W. Finney ,  Michael Howard Hartung ,  Michael Anthony Ko ,  Donald J. Lang ,  Jaishankar Moothedath Menon

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0689

Abstract: A method enables a host processor, which employs variable length (VL) records, to communicate with disk storage which employs fixed length (FL) sectors for storage of the VL records. The method comprises the steps of: a) deriving a first control data structure for an update VL record, the first control data structure including information describing segments of the update VL record; b) determining a disk track that includes a FL sector wherein am old VL record commences that corresponds to the update VL record; c) reading each FL sector in the disk track and creating a control data structure which includes information describing each VL record stored in the disk track; d) substituting in a control data structure for the old VL record that corresponds to the update VL record, information regarding update data from the first control data structure; e) recording in the disk track, data indicated by each control data structure determined in steps c) and d); and f) if the old VL record ends at other than a sector break of a FL sector, reblocking VL records into FL sectors which are recorded thereafter on the disk track. The invention also enables a read action to be accomplished in one rotation of a disk even though it commences at a FL sector that is not at the beginning of a VL record to be accessed.

Abstract translation: 一种方法使得采用可变长度（VL）记录的主机处理器与采用固定长度（FL）扇区的磁盘存储器通信以存储VL记录。 该方法包括以下步骤：a）导出更新VL记录的第一控制数据结构，所述第一控制数据结构包括描述更新VL记录段的信息; b）确定包括FL扇区的磁盘轨道，其中旧的VL记录开始对应于更新VL记录; c）读取磁盘轨道中的每个FL扇区并创建包括描述存储在磁盘轨道中的每个VL记录的信息的控制数据结构; d）用对应于更新VL记录的旧VL记录的控制数据结构替换关于来自第一控制数据结构的更新数据的信息; e）在盘轨道中记录由步骤c）和d）中确定的每个控制数据结构指示的数据; 以及f）如果旧的VL记录在FL扇区的扇区断点之外结束，则将VL记录重新锁定到其后记录在磁盘轨道上的FL扇区中。 本发明还使得能够在盘的一次旋转中实现读取动作，即使其在不在要访问的VL记录的开始处的FL扇区处开始。

公开(公告)号：US5613067A

公开(公告)日：1997-03-18

申请号：US176042

申请日：1993-12-30

Applicant: James T. Brady ,  Damon W. Finney ,  Donald J. Lang ,  George B. Marenin ,  David Nowlen

Inventor： James T. Brady ,  Damon W. Finney ,  Donald J. Lang ,  George B. Marenin ,  David Nowlen

IPC: G06F15/173 ,  H04L29/06 ,  G06F13/20 ,  G06F13/28

CPC classification number: G06F15/17375 ,  H04L29/06

Abstract: A multi-node data processing system implements a method that assures that plural messages are enabled "fair" access to a data stream. Each node includes apparatus for controlling message transmissions and/or receptions from another node over a communication network. The method comprises the steps of: transmitting a routing message from a first destination node to a source node, the routing message signalling a readiness of the destination node to receive a data message; transmitting a first data message to the first destination node from the source node in response to the ready message; transmitting a conditional disconnect message from the first destination node to the source node upon receipt of a predetermined amount (i.e. a "slice") of the first data message. The source node responds to the conditional disconnect message by either (1) disconnecting from the first destination node, and commencing transmission of a slice of a second data message to a second destination node if during transmission of the slice of the first data message, the source node has received a ready message from the second destination node; or (2) continuing transmission of the data message to the first destination node until message end or, following the procedure in (1) if a new ready message is received by the source node from a further destination node, whichever occurs first.

Abstract translation: 多节点数据处理系统实现了一种确保多个消息能够“公平地”访问数据流的方法。 每个节点包括用于通过通信网络控制来自另一个节点的消息传输和/或接收的装置。 该方法包括以下步骤：从第一目的地节点向源节点发送路由消息，所述路由消息发信号通知目的节点接收数据消息的准备状态; 响应于所述就绪消息，从所述源节点向所述第一目的地节点发送第一数据消息; 在接收到所述第一数据消息的预定量（即，“切片”）时，将条件断开消息从所述第一目的地节点发送到所述源节点。 源节点通过（1）从第一目的地节点断开并且如果在第一数据消息的片的传输期间开始将第二数据消息的片段传输到第二目的地节点来响应条件断开消息，则 源节点已经从第二目的地节点接收到就绪消息; 或者（2）数据消息继续传送到第一目的地节点，直到消息结束，或者按照（1）中的源节点从另一个目的地节点接收到新的就绪消息的过程（以先发生者为准）。

公开(公告)号：US5603044A

公开(公告)日：1997-02-11

申请号：US385761

申请日：1995-02-08

Applicant: Narasimhareddy L. Annapareddy ,  Damon W. Finney ,  Michael O. Jenkins ,  Larry B. Kessler ,  Donald J. Lang ,  Song C. Liang ,  David N. Mora ,  David A. Plomgren ,  Peter P. Urbisci ,  Andrew D. Walls

Inventor： Narasimhareddy L. Annapareddy ,  Damon W. Finney ,  Michael O. Jenkins ,  Larry B. Kessler ,  Donald J. Lang ,  Song C. Liang ,  David N. Mora ,  David A. Plomgren ,  Peter P. Urbisci ,  Andrew D. Walls

IPC: G06F15/173 ,  G06F1/18 ,  G06F13/40 ,  G06F9/02

CPC classification number: G06F13/409

Abstract: An interconnection network comprises a pair of backplanes for receiving X pluggable node cards. The pair of backplanes include X backplane connector groups, each backplane connector group adapted to receive mating connectors from a pluggable node card. Each backplane connector group includes X/2 connectors. A first backplane includes first permanent wiring which interconnects a first subset of pairs of connectors between backplane connector groups. A second backplane includes second permanent wiring which interconnects a second subset of pairs of connectors between backplane connector groups. The first permanent wiring and second permanent wiring connect complementary subsets' of pairs of the connectors. A plurality of node cards, each including a card connector group, pluggably mate with the backplane connector groups. Each node card further includes a frontal connector that is adapted to receive a cable interconnection. Each node card includes a processor and a switch module which simultaneously connects the processor to at least plural connectors of a backplane connector group.

Abstract translation: 互连网络包括用于接收X个可插拔节点卡的一对背板。 该对背板包括X个背板连接器组，每个背板连接器组适于从可插拔节点卡接收配对连接器。 每个背板连接器组包括X / 2连接器。 第一背板包括将背板连接器组之间的第一对连接器对互连的第一永久布线。 第二背板包括第二永久布线，其将背板连接器组之间的第二对连接器对互连。 第一个永久布线和第二个永久布线连接了连接器对的互补子集。 多个节点卡，各自包括卡连接器组，可插拔地与背板连接器组配合。 每个节点卡还包括适于接收电缆互连的正面连接器。 每个节点卡包括处理器和开关模块，其将处理器同时连接到背板连接器组的至少多个连接器。

公开(公告)号：US5860088A

公开(公告)日：1999-01-12

申请号：US761719

申请日：1996-12-06

Applicant: Michael T. Benhase ,  James Thomas Brady ,  Damon W. Finney ,  Michael Howard Hartung ,  Michael Anthony Ko ,  Donald J. Lang ,  Jaishankar Moothedath Menon

Inventor： Michael T. Benhase ,  James Thomas Brady ,  Damon W. Finney ,  Michael Howard Hartung ,  Michael Anthony Ko ,  Donald J. Lang ,  Jaishankar Moothedath Menon

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0661 ,  G06F3/0689

Abstract: A method enables a host processor, which employs variable length (VL) records, to transparently communicate with disk storage which employs fixed length (FL) sectors for storage of the VL records. The method comprises the steps of: a) deriving a first control data structure for an update VL record, the first control data structure including information describing segments of the update VL record; b) determining an FL sector wherein an old VL record commences that corresponds to the update VL record; c) if the old VL record commences at other than a sector break of the FL sector, deriving a second control data structure for a portion of a prior VL record that immediately precedes the old VL record and a third control data structure for the old VL record; d) substituting in the third control data structure, information regarding update segments of the update VL record from the first control data structure; and recording in the FL sector determined in c), data indicated by the second control data structure and at least a portion of the update VL record, through use of the third control structure as altered in d).

Abstract translation: 一种方法使得采用可变长度（VL）记录的主机处理器与采用固定长度（FL）扇区的磁盘存储器透明地通信以存储VL记录。 该方法包括以下步骤：a）导出更新VL记录的第一控制数据结构，所述第一控制数据结构包括描述更新VL记录段的信息; b）确定FL扇区，其中旧VL记录开始对应于更新VL记录; c）如果旧的VL记录在FL扇区的扇区之外开始，则导出紧邻旧VL记录之前的先前VL记录的一部分的第二控制数据结构，以及旧VL的第三控制数据结构 记录; d）在第三控制数据结构中替换关于来自第一控制数据结构的更新VL记录的更新段的信息; 并且通过使用在d）中改变的第三控制结构，在c）确定的FL扇区中记录由第二控制数据结构指示的数据和更新VL记录的至少一部分。

公开(公告)号：US5845072A

公开(公告)日：1998-12-01

申请号：US850284

申请日：1997-05-05

Applicant: Damon W. Finney ,  Wen-Jei Ho ,  Mark C. Johnson ,  Donald J. Lang

Inventor： Damon W. Finney ,  Wen-Jei Ho ,  Mark C. Johnson ,  Donald J. Lang

IPC: G06F17/50 ,  G06F13/00

CPC classification number: G06F17/5045

Abstract: A common macro interface between chips that have design features in common and communicate with each other. The common macro interface (CMI) uses VHDL (VHSIC Hardware Description Language) which is the industry standard hardware design language. A common protocol is provided to resolve communication problems and comprises four signals: request; acknowledge request; data acknowledge, and read/write. A freeway system within the interfaces facilitates parallel and pipelining processes and an arbiter (also called a scheduler) is placed in front of every slave resource to control the traffic independently and to avoid traffic collisions from locking the freeway. The freeway is unique for each integrated circuit. Accordingly, macros may be moved from chip to chip without requiring complete system modifications and the effort involved in designing macros common to several chips may be shared.

Abstract translation: 具有共同设计特征并相互通信的芯片之间的通用宏接口。 通用宏接口（CMI）使用行业标准硬件设计语言VHDL（VHSIC硬件描述语言）。 提供通用协议来解决通信问题，包括四个信号：请求; 确认要求; 数据确认和读/写。 接口内的高速公路系统有助于并行和流水线处理，仲裁器（也称为调度器）被放置在每个从属资源的前面，以独立控制流量，避免交通碰撞锁定高速公路。 高速公路对于每个集成电路是独一无二的。 因此，宏可以从芯片移动到芯片，而不需要完整的系统修改，并且可以共享用于设计几个芯片通用的宏的努力。

公开(公告)号：US5057997A

公开(公告)日：1991-10-15

申请号：US310409

申请日：1989-02-13

Applicant: Tai-Lin Chang ,  Paul W. Hunter ,  Donald J. Lang ,  Stephen G. Luning

Inventor： Tai-Lin Chang ,  Paul W. Hunter ,  Donald J. Lang ,  Stephen G. Luning

IPC: G06F9/48 ,  G06F13/26

CPC classification number: G06F13/26

Abstract: In a programmed machine, such as an peripheral controller, programmed operations are executed in a one of several operational contexts. Each context may be initiated by a corresponding interruption signal. Any context which has been activated remains active until quiesced by program execution. One of the active contexts is a current context in which all instruction executions are currently occurring. In each cycle of the programmed machine, all active contexts and received and stored interruption signals, each for respective ones of the contexts, are compared to find the context highest priority context. Such highest priority context is compared with the current context priority for determining whether or not the programmed machine should change current contexts.