Multi-core clocking system with interlocked ‘anti-freeze’ mechanism
    11.
    发明授权
    Multi-core clocking system with interlocked ‘anti-freeze’ mechanism 有权
    具有互锁“防冻”机制的多核心计时系统

    公开(公告)号:US08543860B2

    公开(公告)日:2013-09-24

    申请号:US13059246

    申请日:2008-08-26

    CPC classification number: G06F1/04

    Abstract: A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices.

    Abstract translation: 时钟系统包括多个时钟数据处理装置和时钟控制电路,时钟控制电路控制多个时钟信号的产生以及时钟信号到多个数据处理装置的应用,允许对数据中的至少一个进行时钟 处理设备,同时冻结所有数据处理设备中的至少一个。 一种用于计时多个时钟数据处理装置的方法包括:控制多个时钟信号的产生并控制对多个数据处理装置的时钟信号的应用,允许在冻结期间对数据处理装置中的至少一个进行计时 所有这些数据处理设备中的至少一个。

    MICROCONTROLLER UNIT AND METHOD THEREFOR
    12.
    发明申请
    MICROCONTROLLER UNIT AND METHOD THEREFOR 有权
    微控制器单元及其方法

    公开(公告)号:US20110012650A1

    公开(公告)日:2011-01-20

    申请号:US12596253

    申请日:2007-04-26

    CPC classification number: G06F1/30 G06F1/24 G06F11/0796

    Abstract: A microcontroller unit comprises a reset controller operably coupled to a plurality of logic elements of the microcontroller unit. Low voltage detection logic is operably coupled to the reset controller and arranged to provide a plurality of low voltage interrupt signals to a number of respective logic elements of the microcontroller unit via the reset controller. A method of operating a microcontroller unit is also described.

    Abstract translation: 微控制器单元包括可操作地耦合到微控制器单元的多个逻辑元件的复位控制器。 低电压检测逻辑可操作地耦合到复位控制器并被布置成经由复位控制器向微控制器单元的多个相应逻辑元件提供多个低电压中断信号。 还描述了操作微控制器单元的方法。

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