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11.发明授权Apparatus and method that provides active pull-up and logic translation from one signal mode to another signal mode 有权提供从一种信号模式到另一种信号模式的主动上拉和逻辑转换的装置和方法公开(公告)号：US07446565B2
公开(公告)日：2008-11-04
申请号：US11424533
申请日：2006-06-15
Applicant: Chadwick N. Marak , Jeffrey C Dunnihoo
Inventor： Chadwick N. Marak , Jeffrey C Dunnihoo
IPC: H03K19/094
CPC classification number: H03K19/018521
Abstract: Described is an integrated circuit that causes an input signal having one signal mode with a high state, a low state and a transition state to be dynamically level shifted to another signal mode with a respective high and low state, while minimizing a duration of the transition state of the output signal, wherein the one signal mode and the another signal mode have respectively different high and low state levels.
Abstract translation: 描述了一种集成电路，其将具有高状态，低状态和过渡状态的一个信号模式的输入信号动态地电平移位到具有相应高和低状态的另一信号模式，同时最小化转换的持续时间 输出信号的状态，其中一个信号模式和另一个信号模式分别具有不同的高和低状态电平。
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12.发明申请APPARATUS AND METHOD THAT PROVIDES ACTIVE PULL-UP AND LOGIC TRANSLATION FROM ONE SIGNAL MODE TO ANOTHER SIGNAL MODE 有权提供从一个信号模式到另一个信号模式的主动上拉和逻辑翻译的装置和方法公开(公告)号：US20080007302A1
公开(公告)日：2008-01-10
申请号：US11424533
申请日：2006-06-15
Applicant: Chadwick N. Marak , Jeffrey C. Dunnihoo
Inventor： Chadwick N. Marak , Jeffrey C. Dunnihoo
IPC: H03K19/0175
CPC classification number: H03K19/018521
Abstract: Described is an integrated circuit that causes an input signal having one signal mode with a high state, a low state and a transition state to be dynamically level shifted to another signal mode with a respective high and low state, while minimizing a duration of the transition state of the output signal, wherein the one signal mode and the another signal mode have respectively different high and low state levels.
Abstract translation: 描述了一种集成电路，其将具有高状态，低状态和过渡状态的一个信号模式的输入信号动态地电平移位到具有相应高和低状态的另一信号模式，同时最小化转换的持续时间 输出信号的状态，其中一个信号模式和另一个信号模式分别具有不同的高和低状态电平。
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13.发明授权Process and apparatus for generating power management events in a computer system 失效用于在计算机系统中产生电力管理事件的过程和装置
公开(公告)号：US5708819A
公开(公告)日：1998-01-13
申请号：US541642
申请日：1995-10-10
Applicant: Jeffrey C. Dunnihoo
Inventor： Jeffrey C. Dunnihoo
CPC classification number: G06F1/3203
Abstract: A process and apparatus for reducing power consumption in processor-based system by interrupting the main system power supply during periods of inactivity. Existing input/output circuitry is powered from a constant auxiliary power source to monitor system interrupts which are used to generate power events that control the on/off state of the main system power supply.
Abstract translation: 一种用于通过在不活动期间中断主系统电源来降低基于处理器的系统中的功耗的过程和装置。 现有的输入/输出电路由恒定的辅助电源供电，以监视用于产生控制主系统电源的开/关状态的电源事件的系统中断。
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