公开(公告)号：US20130058175A1

公开(公告)日：2013-03-07

申请号：US13403689

申请日：2012-02-23

Applicant: Chih-Hsin LIN ,  Tsung-Huang CHEN ,  Bing-Shiun WANG ,  Jen-Pin SU

Inventor： Chih-Hsin LIN ,  Tsung-Huang CHEN ,  Bing-Shiun WANG ,  Jen-Pin SU

IPC: G11C8/18

CPC classification number: G11C7/22 ,  G06F13/1689 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1093

Abstract: A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock, and receives a double data rate data from the controller via the common bus according to a data strobe signal from the controller. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory.

Abstract translation: 提供双倍数据速率伪SRAM（DDR PSRAM）。 DDR PSRAM包括数据接收器，存储器和地址解码器。 数据接收器根据时钟通过公共总线从控制器接收第一单个数据速率数据，并且根据来自控制器的数据选通信号经由公共总线从控制器接收双数据速率数据。 地址解码器解码第一单个数据速率数据以获得存储器的地址。 数据接收器将双倍数据速率数据存储到存储器的地址中。