公开(公告)号：US6154794A

公开(公告)日：2000-11-28

申请号：US716951

申请日：1996-09-08

申请人： Karim M. Abdalla ,  Kianoosh Naghshineh ,  James E. Tornes ,  Daniel Yau

发明人： Karim M. Abdalla ,  Kianoosh Naghshineh ,  James E. Tornes ,  Daniel Yau

IPC分类号： G06F3/14 ,  G06F13/14 ,  G06F13/20

CPC分类号： G06F3/14

摘要： A method and apparatus for controlling the flow of information (e.g., graphics primitives, display data, etc.) to an input/output unit within a computer controlled graphics system. The system includes a processor having a first-in-first-out (FIFO) buffer, a separate input/output unit with its FIFO buffer, and a number of intermediate devices (with FIFO buffers) coupled between the input/output unit and the processor for moving input/output data from the processor to the input/output unit. Mechanisms are placed within an intermediate device, very close to the processor, which maintain an accounting of the number of input/output data sent to the input/output unit, but not yet cleared from the input/output unit's buffer. These mechanisms regulate data flow to the input/output unit. By placing these mechanisms close to the processor, rather than within the input/output unit, the system allows a larger portion of the input/output unit's buffer to be utilized for storing input/output data before a processor suspend or interrupt is required. This leads to increased input/output data throughput between the processor and the input/output unit by reducing processor interrupts. The system also includes an efficiently invoked timer mechanism for temporarily suspending the processor from transmitting stores to the input/output unit when the input/output unit and/or the intermediate devices are congested. The processor is not interrupted by an interrupt request until after the timer mechanism times out, allowing the system an opportunity to clear its congestion before a lengthily invoked interrupt is required.

摘要翻译： 一种用于控制计算机控制的图形系统内的输入/输出单元的信息流（例如，图形基元，显示数据等）的方法和装置。 该系统包括具有先进先出（FIFO）缓冲器，具有其FIFO缓冲器的单独输入/输出单元和耦合在输入/输出单元与多个FIFO缓冲器之间的多个中间设备（具有FIFO缓冲器） 处理器，用于将输入/输出数据从处理器移动到输入/输出单元。 机构位于非常接近处理器的中间设备内，其维持对输入/输出单元发送的输入/输出数据的数量的记账，但尚未从输入/输出单元的缓冲器中清除。 这些机制调节到输入/输出单元的数据流。 通过将这些机制放置在处理器附近，而不是在输入/输出单元内，系统允许输入/输出单元的缓冲区的较大部分用于在处理器挂起或中断之前存储输入/输出数据。 这导致通过减少处理器中断来增加处理器和输入/输出单元之间的输入/输出数据吞吐量。 当输入/输出单元和/或中间设备拥塞时，系统还包括有效地调用定时器机制，用于暂时将处理器从发送存储发送到输入/输出单元。 在定时器机制超时之后，处理器不会被中断请求中断，从而允许系统在需要长时间调用中断之前清除其拥塞。

公开(公告)号：US5974456A

公开(公告)日：1999-10-26

申请号：US892879

申请日：1997-07-15

申请人： Kianoosh Naghshineh ,  Daniel E. Lenoski

发明人： Kianoosh Naghshineh ,  Daniel E. Lenoski

IPC分类号： G06F15/173 ,  G06F15/02

CPC分类号： G06F15/17381

摘要： An input/output flow control system for a processor system having an input/output request source (e.g., a processor) and a plurality of input/output request targets (e.g., I/O busses) uses a NACKing (negatively acknowledging) scheme to prevent a common I/O path from becoming blocked due to the blockage of one or more I/O buses. The system includes a flow controller associated with each of the targets for receiving input/output requests from the source, for accepting (ACKing) a request if the intended target can accept the request, and for NACKing a request if the intended target cannot accept the request. The system also includes a processor or source interface for resending the NACKed requests to the intended target and for cooperating with the flow controller so that the NACKed requests are accepted by the flow controller in the proper order.

摘要翻译： 具有输入/输出请求源（例如，处理器）和多个输入/输出请求目标（例如，I / O总线）的处理器系统的输入/输出流控制系统使用NACKing（否定确认）方案 由于一个或多个I / O总线的阻塞，防止普通的I / O路径被阻塞。 该系统包括与每个目标相关联的流量控制器，用于接收来自源的输入/输出请求，用于如果预期目标可接受该请求则接受（确认）请求，以及如果预期目标不能接受请求 请求。 该系统还包括处理器或源接口，用于将NACK请求重新发送到预期目标，并与流控制器协作，以便流控制器以适当顺序接受NACK请求。

公开(公告)号：US5423008A

公开(公告)日：1995-06-06

申请号：US924189

申请日：1992-08-03

申请人： Desmond W. Young ,  Kianoosh Naghshineh ,  William D. Schwaderer

发明人： Desmond W. Young ,  Kianoosh Naghshineh ,  William D. Schwaderer

IPC分类号： G06F13/24 ,  G06F15/17 ,  G06F12/16 ,  G06F12/06

CPC分类号： G06F15/17 ,  G06F13/24

摘要： A high performance shared-bus signal detection mechanism comprises a plurality of access event registers, an address comparator, an event masking component, and a local processor access detector. The comparator component couples to a bus providing access to a shared memory address space. The bus can be used by a single processor or shared by a plurality of processors. A processor loads the address event registers with address base and extent values and type of access notification desired. As addresses and access-type signals appear on the bus, the comparator simultaneously compares the bus information to access event register information to determine if the bus access meets access event register criteria. When matches occur, the comparator emits an appropriate signal to an event masking component. The local processor also loads the event masking component to selectively mask off unwanted event notifications as well as those performed by itself. The event masking component emits signals which feed a general-purpose or special-purpose processors such as interrupt controllers.

摘要翻译： 高性能共享总线信号检测机构包括多个访问事件寄存器，地址比较器，事件屏蔽部件和本地处理器访问检测器。 比较器组件耦合到提供对共享存储器地址空间的访问的总线。 总线可以由单个处理器使用或由多个处理器共享。 处理器将地址事件寄存器加载到所需的地址基址和范围值以及访问通知类型中。 由于地址和访问类型信号出现在总线上，比较器同时比较总线信息以访问事件寄存器信息，以确定总线访问是否满足访问事件寄存器标准。 当发生匹配时，比较器向事件屏蔽组件发出适当的信号。 本地处理器还加载事件屏蔽组件，以选择性地屏蔽不需要的事件通知以及自己执行的事件通知。 事件屏蔽组件发出信号，馈送一个通用或专用处理器，如中断控制器。