公开(公告)号：US12124401B2

公开(公告)日：2024-10-22

申请号：US18155499

申请日：2023-01-17

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Umesh Srikantiah ,  Francesco Gatta ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F13/24

CPC classification number: G06F13/4295 ,  G06F13/24

Abstract: A data communication apparatus comprises a line driver configured to couple the data communication apparatus to a 1-wire serial bus; and a controller configured to: transmit a plurality of synchronization pulses over the 1-wire serial bus after a sequence start condition (SSC) has been transmitted over the 1-wire serial bus, the plurality of synchronization pulses being configured to synchronize one or more receiving devices coupled to the 1-wire serial bus to an untransmitted transmit clock signal; initiate an interrupt handling procedure when the plurality of synchronization pulses is encoded with a first value; and initiate a read transaction or a write transaction with at least one of the one or more receiving devices coupled to the 1-wire serial bus when the plurality of synchronization pulses is encoded with a second value.

公开(公告)号：US12093706B2

公开(公告)日：2024-09-17

申请号：US18186748

申请日：2023-03-20

Applicant: Amazon Technologies, Inc.

Inventor： Barak Wasserstrom ,  Said Bshara ,  Akram Baransi ,  Omri Itach ,  Tal Zilcer

IPC: G06F9/455 ,  G06F13/10 ,  G06F13/24 ,  G06F13/42

CPC classification number: G06F9/455 ,  G06F13/105 ,  G06F13/24 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026

Abstract: Multiple independent endpoint devices can be emulated using a single system on chip (SoC) device. Such a SoC can have multiple cores that can emulate ports according to a specified protocol, such as the peripheral component interconnect express (PCIe) protocol useful for data communications. An emulation agent can manage various aspects of these emulated endpoint devices in software, including serving interrupts for relevant emulated devices according to a determined priority scheme. Interrupts can be registered for each device, and data structures allocated dynamically for a determined number and type(s) of PCIe endpoint devices to be emulated. Each PCIe core on the SoC can function as a separate PCIe endpoint device endpoint for communicating with one or more hosts or other such devices.

公开(公告)号：US20240289292A1

公开(公告)日：2024-08-29

申请号：US18656182

申请日：2024-05-06

Applicant: Apple Inc.

Inventor： Helena Deirdre O'SHEA ,  Camille CHEN ,  Vijay Kumar RAMAMURTHI ,  Alon PAYCHER ,  Matthias SAUER ,  Bernd ADLER

IPC: G06F13/362 ,  G06F11/30 ,  G06F11/34 ,  G06F13/24 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F13/3625 ,  G06F11/3051 ,  G06F11/3409 ,  G06F13/24 ,  G06F13/28 ,  G06F13/4068 ,  G06F2213/0038 ,  G06F2213/40

Abstract: Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity.

公开(公告)号：US12045185B2

公开(公告)日：2024-07-23

申请号：US18296875

申请日：2023-04-06

Applicant: Intel Corporation

Inventor： Philip R. Lantz ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Saurabh Gayen

IPC: G06F13/364 ,  G06F9/50 ,  G06F13/24

CPC classification number: G06F13/364 ,  G06F9/5027 ,  G06F13/24

Abstract: Embodiments of apparatuses, methods, and systems for highly scalable accelerators are described. In an embodiment, an apparatus includes an interface to receive a plurality of work requests from a plurality of clients and a plurality of engines to perform the plurality of work requests. The work requests are to be dispatched to the plurality of engines from a plurality of work queues. The work queues are to store a work descriptor per work request. Each work descriptor is to include all information needed to perform a corresponding work request.

公开(公告)号：US20240232099A9

公开(公告)日：2024-07-11

申请号：US18120827

申请日：2023-03-13

Applicant: Hitachi, Ltd.

Inventor： Kentaro SHIMADA ,  Masanori TAKADA

IPC: G06F12/1081 ,  G06F13/24

CPC classification number: G06F12/1081 ,  G06F13/24

Abstract: A protocol chip transmits the request from the host apparatus to a first processor through a first address translation unit. A first processor transmits a response to the request from the host apparatus, to the protocol chip through the first address translation unit. When the first processor stops processing, an instruction to transmit the request from the host apparatus to a second processor is transmitted to the protocol chip. When receiving the instruction to transmit the request from the host apparatus to the second processor, the protocol chip transmits the request from the host apparatus to the second processor through a second address translation unit. The second processor transmits the response to the request from the host apparatus to the protocol chip through the second address translation unit.

公开(公告)号：US20240232045A9

公开(公告)日：2024-07-11

申请号：US18485837

申请日：2023-10-12

Applicant: Scheidt & Bachmann GmbH

Inventor： Thomas Müller

IPC: G06F11/34 ,  G06F13/24

CPC classification number: G06F11/3495 ,  G06F13/24

Abstract: A mobile ticketing device for a transport vehicle of a passenger transport system includes at least one electrical connector equipment configured to connect the mobile ticketing device to an electrical on-board supply system of the transport vehicle and at least one electrical measuring module configured to measure an electrical parameter applied at the electrical connector equipment. Further included in the mobile ticketing device is at least one generation unit configured to generate at least one measurement data set containing at least one electrical parameter datum about the measured electrical parameter and at least one output module configured to output the generated measurement data set.

公开(公告)号：US20240220309A1

公开(公告)日：2024-07-04

申请号：US18608612

申请日：2024-03-18

Applicant: Marvell Asia Pte, Ltd.

Inventor： Shahe KRAKIRIAN ,  Jason ZEBCHUK ,  Wilson Parkhurst SNYDER II

IPC: G06F9/455 ,  G06F13/24 ,  G06F13/28 ,  G06F13/42

CPC classification number: G06F9/45558 ,  G06F13/24 ,  G06F13/28 ,  G06F13/4282 ,  G06F2009/45579 ,  G06F2213/0026

Abstract: A method and system for flexibly assigning hardware resources to physical and virtual functions in a processor system supporting hardware virtualization is disclosed. The processor system includes a resource virtualization unit which is used to flexibly assign hardware resources to physical functions and also flexibly assign local functions to virtual functions associated with one or more of the physical functions. Thereby, standard PCI software is compatible with the physical functions and any associated virtualized hardware resources that have been flexibly assigned to the virtual and local functions.

公开(公告)号：US12001364B2

公开(公告)日：2024-06-04

申请号：US18124332

申请日：2023-03-21

Applicant: Apple Inc.

Inventor： Helena Deirdre O'Shea ,  Camille Chen ,  Vijay Kumar Ramamurthi ,  Alon Paycher ,  Matthias Sauer ,  Bernd W. Adler

IPC: G06F13/362 ,  G06F11/30 ,  G06F11/34 ,  G06F13/24 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F13/3625 ,  G06F11/3051 ,  G06F11/3409 ,  G06F13/24 ,  G06F13/28 ,  G06F13/4068 ,  G06F2213/0038 ,  G06F2213/40

Abstract: Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity.

公开(公告)号：US20240168895A1

公开(公告)日：2024-05-23

申请号：US18426220

申请日：2024-01-29

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Christian M. Gyllenskog ,  David Aaron Palmer

IPC: G06F13/16 ,  G06F11/30 ,  G06F12/02 ,  G06F12/0868 ,  G06F13/24

CPC classification number: G06F13/1668 ,  G06F11/3037 ,  G06F11/3058 ,  G06F12/0238 ,  G06F12/0868 ,  G06F13/24

Abstract: Various examples are directed to devices and methods involving a host device and a memory system, the memory system comprising a memory controller and a plurality of memory locations. The memory system may send to the host device a first message describing background operations to be performed at the memory system. The memory system may receive from the host device a second message indicating permission to execute the background operations and may begin to execute at least one background operation.

公开(公告)号：US11977668B2

公开(公告)日：2024-05-07

申请号：US17348352

申请日：2021-06-15

Applicant: Huawei Technologies Co., Ltd.

Inventor： Ben-Shahar Belkar

IPC: G06F21/85 ,  G06F13/24 ,  G06F16/23 ,  G06F21/56

CPC classification number: G06F21/85 ,  G06F13/24 ,  G06F16/2379 ,  G06F21/566 ,  G06F21/567 ,  G06F2221/034

Abstract: The present disclosure relates to a device for supporting Input/Output (I/O) channel protection. The device maintains one or more channel protection enclaves (CPEs), wherein each CPE is associated with a different I/O channel, wherein each I/O channel is associated with a different address space of a memory, and wherein each CPE is allocated verification information comprising the address space associated with its associated I/O channel. The device further receives a transaction on a given I/O channel, the transaction comprising access information including one or more target addresses. Moreover, the device determines a correlation of the transaction's access information and the verification information of the CPE associated with the given I/O channel, and allows or aborts execution of the transaction, based on whether the determined correlation meets a predefined criterion.