公开(公告)号：US6147893A

公开(公告)日：2000-11-14

申请号：US238531

申请日：1999-01-27

Applicant: Kwo-Jen Liu

Inventor： Kwo-Jen Liu

IPC: G11C17/12 ,  G11C17/00

CPC classification number: G11C17/12

Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

Abstract translation: 一种在低工作电压下具有高速差分感测的可编程只读存储器的方法和装置。 在一个实施例中，可编程存储单元由字线，位线和晶体管组成。 表示单个二进制数位（位）的晶体管具有耦合到字线的栅极，耦合到位线的漏极和能够被编程以提供逻辑电平0并且逻辑电平为1的源。通过 对晶体管的源极进行编程，逻辑电平0和逻辑电平1状态之间的位线几乎相等。

公开(公告)号：US20090257273A1

公开(公告)日：2009-10-15

申请号：US12422078

申请日：2009-04-10

Applicant: WEI-CHIANG SHIH ,  CHEN-HAO PO ,  KWO-JEN LIU

Inventor： WEI-CHIANG SHIH ,  CHEN-HAO PO ,  KWO-JEN LIU

IPC: G11C11/24 ,  G11C11/00 ,  G11C7/00

CPC classification number: G11C11/412 ,  G11C11/413

Abstract: A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N type switch has a control terminal connected to the word line and a first terminal connected to an inverted bit line. The first storage node has a first terminal connected to a second terminal of the first N type switch. The second storage node has a first terminal connected to a second terminal of the second N type switch.

Abstract translation: SRAM单元结构包括第一N型交换机，第二N型交换机，第一存储节点和第二存储节点。 第一N型开关具有连接到字线的控制端子和连接到位线的第一端子。 第二N型开关具有连接到字线的控制端子和连接到反相位线的第一端子。 第一存储节点具有连接到第一N型交换机的第二终端的第一终端。 第二存储节点具有连接到第二N型交换机的第二终端的第一终端。

公开(公告)号：US06806142B1

公开(公告)日：2004-10-19

申请号：US10604263

申请日：2003-07-07

Applicant: An-Ru Cheng ,  Kwo-Jen Liu ,  Chih-Hung Chen

Inventor： An-Ru Cheng ,  Kwo-Jen Liu ,  Chih-Hung Chen

IPC: H01L218234

CPC classification number: H01L27/11226 ,  H01L27/112

Abstract: A method for manufacturing a ROM device includes a semiconductor substrate having an array of field-effect transistors within a ROM region. A first dielectric layer covers the array and all transistors are initially in an “ON” state. A second dielectric layer covers at least one layer of metal interconnection formed over the first dielectric layer. The bit lines do not overlap the transistor-sources. A coding photoresist layer is formed on the second dielectric layer and is patterned to form a plurality of apertures defining exposure windows exposing underlying field-effect transistors to be coded permanently to an “OFF” state. A code etching back process is implemented using the photoresist layer as a mask to etch the first and second dielectric layers, the sources of the MOSFETs, and a portion of the substrate through the exposure windows to form a deep trench, disconnecting the coded MOSFETs from the source lines.

Abstract translation: 一种用于制造ROM器件的方法包括：具有ROM区域内的场效应晶体管阵列的半导体衬底。 第一介电层覆盖阵列，并且所有晶体管最初处于“接通”状态。 第二介电层覆盖形成在第一介电层上的至少一层金属互连层。 位线不与晶体管源重叠。 编码光致抗蚀剂层形成在第二电介质层上，并且被图案化以形成限定曝光窗口的多个孔，暴露下来的场效应晶体管被永久地编码为“关”状态。 使用光致抗蚀剂层作为掩模来实现代码蚀刻反向工艺，以通过曝光窗口蚀刻第一和第二介电层，MOSFET的源和衬底的一部分，以形成深沟槽，从而将编码的MOSFET从 源码行。