公开(公告)号：US06806142B1

公开(公告)日：2004-10-19

申请号：US10604263

申请日：2003-07-07

Applicant: An-Ru Cheng ,  Kwo-Jen Liu ,  Chih-Hung Chen

Inventor： An-Ru Cheng ,  Kwo-Jen Liu ,  Chih-Hung Chen

IPC: H01L218234

CPC classification number: H01L27/11226 ,  H01L27/112

Abstract: A method for manufacturing a ROM device includes a semiconductor substrate having an array of field-effect transistors within a ROM region. A first dielectric layer covers the array and all transistors are initially in an “ON” state. A second dielectric layer covers at least one layer of metal interconnection formed over the first dielectric layer. The bit lines do not overlap the transistor-sources. A coding photoresist layer is formed on the second dielectric layer and is patterned to form a plurality of apertures defining exposure windows exposing underlying field-effect transistors to be coded permanently to an “OFF” state. A code etching back process is implemented using the photoresist layer as a mask to etch the first and second dielectric layers, the sources of the MOSFETs, and a portion of the substrate through the exposure windows to form a deep trench, disconnecting the coded MOSFETs from the source lines.

Abstract translation: 一种用于制造ROM器件的方法包括：具有ROM区域内的场效应晶体管阵列的半导体衬底。 第一介电层覆盖阵列，并且所有晶体管最初处于“接通”状态。 第二介电层覆盖形成在第一介电层上的至少一层金属互连层。 位线不与晶体管源重叠。 编码光致抗蚀剂层形成在第二电介质层上，并且被图案化以形成限定曝光窗口的多个孔，暴露下来的场效应晶体管被永久地编码为“关”状态。 使用光致抗蚀剂层作为掩模来实现代码蚀刻反向工艺，以通过曝光窗口蚀刻第一和第二介电层，MOSFET的源和衬底的一部分，以形成深沟槽，从而将编码的MOSFET从 源码行。

公开(公告)号：US20050049812A1

公开(公告)日：2005-03-03

申请号：US10709425

申请日：2004-05-05

Applicant: Jie-Hong Wang ,  Kai-Jen Ko ,  An-Ru Cheng

Inventor： Jie-Hong Wang ,  Kai-Jen Ko ,  An-Ru Cheng

IPC: G01R31/28 ,  G06F19/00 ,  G01R31/00

CPC classification number: G01R31/2853

Abstract: A method for testing latch-up phenomenon of a chip is provided. The chip is tested on a test platform, the test platform storing a test program of the chip for testing the chip. The method includes (a) obtaining the test program of the chip tested on the test platform, (b) obtaining pin data of the chip by the test program of the chip, (c) setting up an input pin of the chip with an initial value, and (d) providing a test current to the pin of the chip, and then measuring the current between a power end and a ground end of the chip to see if it exceeds a first predetermined value.

Abstract translation: 提供了一种用于测试芯片闭锁现象的方法。 该芯片在测试平台上进行测试，测试平台存储芯片测试程序，用于测试芯片。 该方法包括：（a）获得在测试平台上测试的芯片的测试程序，（b）通过芯片的测试程序获取芯片的引脚数据，（c）以初始化的方式设置芯片的输入引脚 值，以及（d）向芯片的引脚提供测试电流，然后测量芯片的电源端和接地端之间的电流，以查看其是否超过第一预定值。

公开(公告)号：US20060123375A1

公开(公告)日：2006-06-08

申请号：US11341481

申请日：2006-01-30

Applicant: An-Ru Cheng ,  Chang-Song Lin ,  Tzu-Chun Liu ,  Huan-Yung Tseng

Inventor： An-Ru Cheng ,  Chang-Song Lin ,  Tzu-Chun Liu ,  Huan-Yung Tseng

IPC: G06F17/50 ,  G01R31/28

CPC classification number: G01R31/318538 ,  G01R31/31855

Abstract: An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.

公开(公告)号：US07089137B2

公开(公告)日：2006-08-08

申请号：US10709425

申请日：2004-05-05

Applicant: Jie-Hong Wang ,  Kai-Jen Ko ,  An-Ru Cheng

Inventor： Jie-Hong Wang ,  Kai-Jen Ko ,  An-Ru Cheng

IPC: G01R31/14

CPC classification number: G01R31/2853

Abstract: A method for testing latch-up phenomenon of a chip is provided. The chip is tested on a test platform, the test platform storing a test program of the chip for testing the chip. The method includes (a) obtaining the test program of the chip tested on the test platform, (b) obtaining pin data of the chip by the test program of the chip, (c) setting up an input pin of the chip with an initial value, and (d) providing a test current to the pin of the chip, and then measuring the current between a power end and a ground end of the chip to see if it exceeds a first predetermined value.

Abstract translation: 提供了一种用于测试芯片闭锁现象的方法。 该芯片在测试平台上进行测试，测试平台存储芯片测试程序，用于测试芯片。 该方法包括：（a）获得在测试平台上测试的芯片的测试程序，（b）通过芯片的测试程序获取芯片的引脚数据，（c）以初始化的方式设置芯片的输入引脚 值，以及（d）向芯片的引脚提供测试电流，然后测量芯片的电源端和接地端之间的电流，以查看其是否超过第一预定值。

公开(公告)号：US06756275B1

公开(公告)日：2004-06-29

申请号：US10249286

申请日：2003-03-28

Applicant: Kwo-Jen Liu ,  Chih-Hung Chen ,  An-Ru Cheng

Inventor： Kwo-Jen Liu ,  Chih-Hung Chen ,  An-Ru Cheng

IPC: H01L218236

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A method for manufacturing a ROM device includes a semiconductor substrate having an array of field-effect transistors within a ROM region. A first dielectric layer covers the array of field-effect transistors. All of the field-effect transistors are initially in an “ON” state having a threshold voltage at a first value. At least one layer of metal interconnection is formed over the first dielectric layer within the ROM region and Is covered by a second dielectric layer. A coding photoresist layer is formed on the second dielectric layer and patterned to form a plurality of apertures defining exposure windows. Using the patterning coding photoresist layer as a dielectric etching and implantation hard mask, the underlying field-effect transistors to be coded permanently to a logic “OFF” state through the apertures, thereby raising the threshold voltage of the field-effect transistors to a second value.

Abstract translation: 一种用于制造ROM器件的方法包括：具有ROM区域内的场效应晶体管阵列的半导体衬底。 第一介电层覆盖场效应晶体管阵列。 所有场效应晶体管初始处于具有第一值的阈值电压的“导通”状态。 在ROM区域内的第一介电层上形成至少一层金属互连，并被第二介电层覆盖。 编码光致抗蚀剂层形成在第二电介质层上并被图案化以形成限定曝光窗口的多个孔。 使用图案化编码光致抗蚀剂层作为电介质蚀刻和注入硬掩模，下面的场效应晶体管将通过孔径永久地编码为逻辑“关”状态，从而将场效应晶体管的阈值电压提高到第二 值。